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Line 81... |
ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_MCR) == 0x00); //4
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// ASSERT(getreg (UART_LSR) == 0x60); //5
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// ASSERT(getreg (UART_LSR) == 0x60); //5
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// ASSERT(getreg (UART_MSR) == 0xff); //6
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// ASSERT(getreg (UART_MSR) == 0x00); //6
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ASSERT(getreg (UART_MSR) == 0x00); //6
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLH) == 0x00); //1
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ASSERT(getreg (UART_DLH) == 0x00); //1
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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}
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}
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{ /* test if status registers are read only */
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{ /* test if status registers are read only */
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unsigned long tmp;
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/*unsigned long tmp;
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int i;
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int i;
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tmp = getreg (UART_LSR);
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tmp = getreg (UART_LSR);
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setreg (UART_LSR, ~tmp);
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setreg (UART_LSR, ~tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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for (i = 0; i < 9; i++) {
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setreg (UART_LSR, 1 << i);
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ASSERT(getreg (UART_LSR) == tmp);
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}
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for (i = 0; i < 9; i++) {
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setreg (UART_LSR, 1 << i);
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ASSERT(getreg (UART_LSR) == tmp);
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}
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*/
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/*tmp = getreg (UART_MSR);
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/*tmp = getreg (UART_MSR);
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setreg (UART_MSR, ~tmp);
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setreg (UART_MSR, ~tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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