| Line 39... |
Line 39... |
#define LSR_BREAK (0x10)
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#define LSR_BREAK (0x10)
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#define LSR_TXFE (0x20)
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#define LSR_TXFE (0x20)
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#define LSR_TXE (0x40)
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#define LSR_TXE (0x40)
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#define LSR_ERR (0x80)
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#define LSR_ERR (0x80)
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#define UART_INT_LINE 4 /* To which interrupt is uart connected */
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#define UART_INT_LINE 15 /* To which interrupt is uart connected */
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/* fails if x is false */
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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/* Waits a few cycles that uart can prepare its data */
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/* Waits a few cycles that uart can prepare its data */
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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| Line 348... |
Line 348... |
/* Receive a break */
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/* Receive a break */
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send_char ('!');
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send_char ('!');
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MARK();
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MARK();
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while (!((x = getreg (UART_LSR)) & LSR_DR));
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while (!((x = getreg (UART_LSR)) & LSR_DR));
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/* we should receive zero character with broken frame and break bit should be set */
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/* we should receive zero character with broken frame and break bit should be set */
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printf("[%x]\n", (LSR_DR | LSR_FE | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
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printf("[%x]\n", (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
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ASSERT (x == (LSR_DR | LSR_FE | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
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ASSERT (x == (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
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ASSERT (getreg (UART_RBR) == 0);
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ASSERT (getreg (UART_RBR) == 0);
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MARK();
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MARK();
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/* Send a # to release break */
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/* Send a # to release break */
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setreg (UART_THR, '#');
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setreg (UART_THR, '#');
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| Line 381... |
Line 381... |
/* Receive a break */
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/* Receive a break */
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send_char ('#');
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send_char ('#');
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while (!((x = getreg (UART_LSR)) & LSR_DR));
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while (!((x = getreg (UART_LSR)) & LSR_DR));
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/* we should receive zero character with broken frame and break bit
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/* we should receive zero character with broken frame and break bit
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should not be set, because we cleared it */
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should not be set, because we cleared it */
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printf("[%x:%x]\n", x, (LSR_DR | LSR_FE | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
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printf("[%x:%x]\n", x, (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
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ASSERT (x == (LSR_DR | LSR_FE | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
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ASSERT (x == (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
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ASSERT (getreg (UART_RBR) == 0);
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ASSERT (getreg (UART_RBR) == 0);
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MARK();
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MARK();
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send_char ('?');
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send_char ('?');
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MARK();
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MARK();
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while (!(getreg (UART_LSR) & LSR_DR));
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while (!(getreg (UART_LSR) & LSR_DR));
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| Line 464... |
Line 464... |
setreg (UART_LCR, LCR_DIVL);
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_DLH, 2 >> 8);
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setreg (UART_DLH, 2 >> 8);
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setreg (UART_DLL, 2 & 0xff);
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setreg (UART_DLL, 2 & 0xff);
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setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
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setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
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MARK();
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MARK();
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while (!(getreg (UART_LSR) & 1)); /* Receive 'x' char */
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getreg (UART_RBR);
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MARK();
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send_char ('T');
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send_char ('T');
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while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
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while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
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MARK();
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MARK();
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printf ("OK\n");
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printf ("OK\n");
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| Line 484... |
Line 487... |
setreg (UART_LCR, LCR_DIVL);
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_DLH, 6 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
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setreg (UART_DLH, 6 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
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setreg (UART_DLL, 6 & 0xff);
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setreg (UART_DLL, 6 & 0xff);
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setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
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setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
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ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
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setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
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setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
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setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
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setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
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ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
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MARK();
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MARK();
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#if 0
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while (!int_cnt); /* Clear previous THR interrupt */
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ASSERT (--int_cnt == 0);
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ASSERT (int_iir == 0xc2);
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ASSERT ((int_lsr & 0xbe) == 0x20);
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MARK();
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#endif
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/* I am configured - start interrupt test */
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/* I am configured - start interrupt test */
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send_char ('I');
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send_char ('I');
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while (!int_cnt); /* Wait for THR to be empty */
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while (!int_cnt); /* Wait for THR to be empty */
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ASSERT (--int_cnt == 0);
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ASSERT (--int_cnt == 0);
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ASSERT (int_iir == 0xc2);
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ASSERT (int_iir == 0xc2);
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| Line 605... |
Line 616... |
MARK();
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MARK();
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while (!int_cnt); /* Wait for break interrupt */
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while (!int_cnt); /* Wait for break interrupt */
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ASSERT (--int_cnt == 0);
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ASSERT (--int_cnt == 0);
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ASSERT (int_iir == 0xc6);
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ASSERT (int_iir == 0xc6);
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ASSERT (int_lsr == 0xf9); /* BE flag should be set */
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ASSERT (int_lsr == 0xf1); /* BE flag should be set */
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ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
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ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
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MARK();
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MARK();
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recv_char (0);
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recv_char (0);
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MARK();
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MARK();
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| Line 767... |
Line 778... |
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register_test ();
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register_test ();
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init_8n1 ();
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init_8n1 ();
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// send_recv_test ();
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// send_recv_test ();
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// break_test ();
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// break_test ();
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// different_modes_test ();
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different_modes_test ();
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// interrupt_test ();
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interrupt_test ();
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// control_register_test ();
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control_register_test ();
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line_error_test ();
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line_error_test ();
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/* loopback_test ();
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/* loopback_test ();
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modem_test ();
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modem_test ();
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modem_error_test ();*/
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modem_error_test ();*/
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