OpenCores

URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [board.h] - Diff between revs 970 and 972

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 970	Rev 972
Line 8...	Line 8...
`#define SDRAM_BASE_ADDR 0x00000000`	`#define SDRAM_BASE_ADDR 0x00000000`
`#define SDRAM_TMS_VAL 0x19220057`	`#define SDRAM_TMS_VAL 0x19220057`


`#define UART_BASE 0x90000000`	`#define UART_BASE 0x90000000`
`#define UART_IRQ 19`	`#define UART_IRQ 2`
`#define ETH_BASE 0x92000000`	`#define ETH_BASE 0x92000000`
`#define ETH_IRQ 15`	`#define ETH_IRQ 4`
`#define KBD_BASE_ADD 0x94000000`	`#define KBD_BASE_ADD 0x94000000`
`#define KBD_IRQ 5`	`#define KBD_IRQ 5`
`#define MC_BASE_ADDR 0x93000000`	`#define MC_BASE_ADDR 0x93000000`
`#define DMA_BASE 0xb8000000`	`#define DMA_BASE 0xb8000000`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.