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/* Cache test */
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/* Cache test */
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#include "support.h"
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#include "support.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#define MEM_RAM 0x40000000
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#define MEM_RAM 0x40100000
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/* Number of IC sets (power of 2) */
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/* Number of IC sets (power of 2) */
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#define IC_SETS 512
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#define IC_SETS 512
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#define DC_SETS 512
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#define DC_SETS 512
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#define REG32(add) *((volatile unsigned long *)(add))
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#define REG32(add) *((volatile unsigned long *)(add))
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extern void (*jalr)(void);
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extern void (*jalr)(void);
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extern void (*jr)(void);
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extern void (*jr)(void);
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/* Index on jump table */
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unsigned long jump_indx;
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/* Jump address table */
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unsigned long jump_add[15*IC_WAYS];
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void dummy();
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void dummy();
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void jump_and_link(void)
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void jump_and_link(void)
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{
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{
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asm("_jalr:");
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asm("_jalr:");
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void jump(void)
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void jump(void)
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{
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{
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asm("_jr:");
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asm("_jr:");
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/* Read and increment index */
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/* Read and increment index */
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asm("l.lwz\t\tr3,0(r0)");
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asm("l.lwz\t\tr3,0(r11)");
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asm("l.addi\t\tr3,r3,4");
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asm("l.addi\t\tr3,r3,4");
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asm("l.sw\t\t0(r0),r3");
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asm("l.sw\t\t0(r11),r3");
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/* Load next executin address from table */
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/* Load next executin address from table */
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asm("l.lwz\t\tr3,0(r3)");
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asm("l.lwz\t\tr3,0(r3)");
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/* Jump to that address */
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/* Jump to that address */
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asm("l.jr\t\tr3") ;
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asm("l.jr\t\tr3") ;
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/* Report that we succeeded */
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/* Report that we succeeded */
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memcpy((void *)add, (void *)&jr, 24);
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memcpy((void *)add, (void *)&jr, 24);
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}
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}
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void call(unsigned long add)
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void call(unsigned long add)
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{
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{
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asm("l.movhi\tr11,hi(_jump_indx)" : :);
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asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
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asm("l.jr\t\t%0" : : "r" (add) : "r11");
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asm("l.jr\t\t%0" : : "r" (add) : "r11");
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asm("l.nop" : :);
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asm("l.nop" : :);
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}
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}
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void icache_enable(void)
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void icache_enable(void)
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int dc_test(void)
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int dc_test(void)
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{
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{
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int i;
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int i;
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unsigned long base, add, ul;
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unsigned long base, add, ul;
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base = (((unsigned long)&dummy / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
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base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
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dcache_enable();
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dcache_enable();
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/* Cache miss r */
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/* Cache miss r */
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add = base;
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add = base;
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int ic_test(void)
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int ic_test(void)
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{
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{
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int i;
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int i;
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unsigned long base, add;
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unsigned long base, add;
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base = (((unsigned long)&dummy / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
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base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
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/* Copy jr to various location */
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/* Copy jr to various location */
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add = base;
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add = base;
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for(i = 0; i < IC_WAYS; i++) {
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for(i = 0; i < IC_WAYS; i++) {
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copy_jr(add);
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copy_jr(add);
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/* Load execution table which starts at address 4 (at address 0 is table index) */
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/* Load execution table which starts at address 4 (at address 0 is table index) */
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add = base;
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add = base;
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for(i = 0; i < IC_WAYS; i++) {
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for(i = 0; i < IC_WAYS; i++) {
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/* Cache miss */
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/* Cache miss */
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REG32(0x3c*i + 0x04) = add + 2*IC_BLOCK_SIZE + 4;
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jump_add[15*i + 0] = add + 2*IC_BLOCK_SIZE + 4;
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REG32(0x3c*i + 0x08) = add + 4*IC_BLOCK_SIZE + 8;
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jump_add[15*i + 1] = add + 4*IC_BLOCK_SIZE + 8;
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REG32(0x3c*i + 0x0c) = add + 6*IC_BLOCK_SIZE + 12;
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jump_add[15*i + 2] = add + 6*IC_BLOCK_SIZE + 12;
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/* Cache hit/miss */
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/* Cache hit/miss */
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REG32(0x3c*i + 0x10) = add;
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jump_add[15*i + 3] = add;
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REG32(0x3c*i + 0x14) = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
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jump_add[15*i + 4] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
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REG32(0x3c*i + 0x18) = add + 2*IC_BLOCK_SIZE + 4;
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jump_add[15*i + 5] = add + 2*IC_BLOCK_SIZE + 4;
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REG32(0x3c*i + 0x1c) = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
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jump_add[15*i + 6] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
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REG32(0x3c*i + 0x20) = add + 4*IC_BLOCK_SIZE + 8;
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jump_add[15*i + 7] = add + 4*IC_BLOCK_SIZE + 8;
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REG32(0x3c*i + 0x24) = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
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jump_add[15*i + 8] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
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REG32(0x3c*i + 0x28) = add + 6*IC_BLOCK_SIZE + 12;
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jump_add[15*i + 9] = add + 6*IC_BLOCK_SIZE + 12;
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REG32(0x3c*i + 0x2c) = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
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jump_add[15*i + 10] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
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/* Cache hit */
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/* Cache hit */
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REG32(0x3c*i + 0x30) = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
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jump_add[15*i + 11] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
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REG32(0x3c*i + 0x34) = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
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jump_add[15*i + 12] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
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REG32(0x3c*i + 0x38) = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
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jump_add[15*i + 13] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
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REG32(0x3c*i + 0x3c) = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
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jump_add[15*i + 14] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
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add += IC_SETS*IC_BLOCK_SIZE;
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add += IC_SETS*IC_BLOCK_SIZE;
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}
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}
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/* Go home */
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/* Go home */
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REG32(0x3c*i + 4) = (unsigned long)&jalr;
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jump_add[15*i] = (unsigned long)&jalr;
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/* Initilalize table index */
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/* Initilalize table index */
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REG32(0) = 0;
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jump_indx = &jump_add[0];
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icache_enable();
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icache_enable();
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/* Go */
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/* Go */
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call(base);
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call(base);
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