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/* Cache test */
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/* Cache test */
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#include "support.h"
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#include "support.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#define MEM_RAM 0x40100000
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#define OR1KSIM 1
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#ifdef OR1KSIM
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#undef UART
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#else
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#define UART 1
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#endif
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#define MEM_RAM 0x00100000
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/* Number of IC sets (power of 2) */
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/* Number of IC sets (power of 2) */
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#define IC_SETS 512
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#define IC_SETS 256
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#define DC_SETS 512
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#define DC_SETS 256
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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#define IC_BLOCK_SIZE 16
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#define IC_BLOCK_SIZE 16
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#define DC_BLOCK_SIZE 16
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#define DC_BLOCK_SIZE 16
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/* Memory access macros */
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/* Memory access macros */
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#define REG8(add) *((volatile unsigned char *)(add))
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#define REG8(add) *((volatile unsigned char *)(add))
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#define REG16(add) *((volatile unsigned short *)(add))
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#define REG16(add) *((volatile unsigned short *)(add))
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#define REG32(add) *((volatile unsigned long *)(add))
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#define REG32(add) *((volatile unsigned long *)(add))
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#if UART
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#include "uart.h"
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#define IN_CLK 20000000
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#define UART_BASE 0x9c000000
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#define UART_BAUD_RATE 9600
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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#define WAIT_FOR_XMITR \
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do { \
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lsr = REG8(UART_BASE + UART_LSR); \
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} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
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#define WAIT_FOR_THRE \
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do { \
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lsr = REG8(UART_BASE + UART_LSR); \
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} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
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#define CHECK_FOR_CHAR \
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(REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
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#define WAIT_FOR_CHAR \
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do { \
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lsr = REG8(UART_BASE + UART_LSR); \
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} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
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#define UART_TX_BUFF_LEN 32
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#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
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#define print_n(x) \
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{ \
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uart_putc(s[((x) >> 28) & 0x0f]); \
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uart_putc(s[((x) >> 24) & 0x0f]); \
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uart_putc(s[((x) >> 20) & 0x0f]); \
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uart_putc(s[((x) >> 16) & 0x0f]); \
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uart_putc(s[((x) >> 12) & 0x0f]); \
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uart_putc(s[((x) >> 8) & 0x0f]); \
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uart_putc(s[((x) >> 4) & 0x0f]); \
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uart_putc(s[((x) >> 0) & 0x0f]); \
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}
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const char s[] = "0123456789abcdef";
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void uart_init(void)
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{
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int devisor;
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/* Reset receiver and transmiter */
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REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
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/* Disable all interrupts */
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REG8(UART_BASE + UART_IER) = 0x00;
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/* Set 8 bit char, 1 stop bit, no parity */
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REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
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/* Set baud rate */
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devisor = IN_CLK/(16 * UART_BAUD_RATE);
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REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
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REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;
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REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;
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REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
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return;
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}
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static inline void uart_putc(char c)
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{
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unsigned char lsr;
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WAIT_FOR_THRE;
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REG8(UART_BASE + UART_TX) = c;
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if(c == '\n') {
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WAIT_FOR_THRE;
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REG8(UART_BASE + UART_TX) = '\r';
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}
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WAIT_FOR_XMITR;
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}
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static inline void print_str(char *str)
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{
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while(*str != 0) {
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uart_putc(*str);
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str++;
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}
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}
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static inline char uart_getc()
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{
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unsigned char lsr;
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char c;
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WAIT_FOR_CHAR;
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c = REG8(UART_BASE + UART_RX);
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return c;
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}
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#endif
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extern void ic_enable(void);
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extern void ic_disable(void);
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extern void dc_enable(void);
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extern void dc_disable(void);
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extern void dc_inv(void);
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extern unsigned long ic_inv_test(void);
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extern unsigned long dc_inv_test(unsigned long);
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extern void (*jalr)(void);
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extern void (*jalr)(void);
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extern void (*jr)(void);
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extern void (*jr)(void);
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/* Index on jump table */
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/* Index on jump table */
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unsigned long jump_indx;
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unsigned long jump_indx;
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/* Load next executin address from table */
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/* Load next executin address from table */
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asm("l.lwz\t\tr3,0(r3)");
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asm("l.lwz\t\tr3,0(r3)");
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/* Jump to that address */
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/* Jump to that address */
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asm("l.jr\t\tr3") ;
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asm("l.jr\t\tr3") ;
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/* Report that we succeeded */
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/* Report that we succeeded */
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asm("l.nop\t2");
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asm("l.nop\t0");
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}
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}
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void copy_jr(unsigned long add)
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void copy_jr(unsigned long add)
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{
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{
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memcpy((void *)add, (void *)&jr, 24);
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memcpy((void *)add, (void *)&jr, 24);
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asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
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asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
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asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");
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asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");
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asm("l.nop" : :);
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asm("l.nop" : :);
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}
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}
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void icache_enable(void)
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{
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unsigned long add;
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/* First invalidate the cache. As at this point cache is disabled,
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the cache acts as it contains image of lowest memory block */
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for(add = 1; add <= IC_SIZE; add += IC_BLOCK_SIZE)
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mtspr(SPR_ICBIR, add);
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
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}
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void dcache_enable(void)
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{
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unsigned long add;
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/* First invalidate the cache. As at this point cache is disabled,
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the cache acts as it contains image of lowest memory block */
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for(add = 1; add <= DC_SIZE; add += DC_BLOCK_SIZE)
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mtspr(SPR_DCBIR, add);
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
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}
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void icache_disable(void)
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{
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/* This is write trough cache so we dont have to flush it */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
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}
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void dcache_disable(void)
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{
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/* This is write trough cache so we dont have to flush it */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
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}
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int dc_test(void)
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int dc_test(void)
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{
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{
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int i;
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int i;
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unsigned long base, add, ul;
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unsigned long base, add, ul;
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base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
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base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
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dcache_enable();
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dc_enable();
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/* Cache miss r */
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/* Cache miss r */
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add = base;
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add = base;
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for(i = 0; i < DC_WAYS; i++) {
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for(i = 0; i < DC_WAYS; i++) {
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ul = REG32(add);
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ul = REG32(add);
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ul = REG32(add + DC_BLOCK_SIZE);
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ul = REG32(add + DC_BLOCK_SIZE + 4);
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ul = REG32(add + 2*DC_BLOCK_SIZE);
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ul = REG32(add + 2*DC_BLOCK_SIZE + 8);
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ul = REG32(add + 3*DC_BLOCK_SIZE);
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ul = REG32(add + 3*DC_BLOCK_SIZE + 12);
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add += DC_SETS*DC_BLOCK_SIZE;
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add += DC_SETS*DC_BLOCK_SIZE;
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}
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}
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/* Cache hit w */
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/* Cache hit w */
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add = base;
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add = base;
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for(i = 0; i < DC_WAYS; i++) {
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for(i = 0; i < DC_WAYS; i++) {
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REG32(add + 0) = 0x00000001;
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REG32(add + 0) = 0x00000001;
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REG32(add + 4) = 0x00000000;
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REG32(add + 8) = 0x00000000;
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REG32(add + 12) = 0x00000000;
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REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000;
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REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
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REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
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REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000;
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REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000;
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REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000;
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REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000;
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REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
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REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
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REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000;
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REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000;
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REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000;
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REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000;
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REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
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REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
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add += DC_SETS*DC_BLOCK_SIZE;
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add += DC_SETS*DC_BLOCK_SIZE;
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}
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}
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/* Cache hit r/w */
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/* Cache hit r/w */
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Line 273... |
REG16(add+ DC_BLOCK_SIZE - 16) +
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REG16(add+ DC_BLOCK_SIZE - 16) +
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REG16(add + 2*DC_BLOCK_SIZE + 14);
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REG16(add + 2*DC_BLOCK_SIZE + 14);
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add += DC_SETS*DC_BLOCK_SIZE;
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add += DC_SETS*DC_BLOCK_SIZE;
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}
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}
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dcache_disable();
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dc_disable();
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return ul;
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return ul;
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}
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}
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int ic_test(void)
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int ic_test(void)
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/* Go home */
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/* Go home */
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jump_add[15*i] = (unsigned long)&jalr;
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jump_add[15*i] = (unsigned long)&jalr;
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/* Initilalize table index */
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/* Initilalize table index */
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jump_indx = &jump_add[0];
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jump_indx = (unsigned long)&jump_add[0];
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icache_enable();
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ic_enable();
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/* Go */
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/* Go */
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call(base);
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call(base);
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icache_disable();
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ic_disable();
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return 0xdeaddead;
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return 0;
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}
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}
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int main(void)
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int main(void)
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{
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{
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int rc;
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unsigned long rc, ret = 0;
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#ifdef UART
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/* Initialize controller */
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uart_init();
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#endif
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#ifdef UART
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print_str("DC test : ");
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#endif
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rc = dc_test();
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rc = dc_test();
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ret += rc;
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#ifdef UART
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print_n(rc+0xdeaddca1);
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print_str("\n");
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#else
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report(rc + 0xdeaddca1);
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report(rc + 0xdeaddca1);
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#endif
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/* Be aware that this test doesn't report result troug report call.
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#ifndef OR1KSIM
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It writes to spr 0x1234 directly (in jump function)!!!
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#ifdef UART
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print_str("DC invalidate test : ");
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This test can not be run on or1ksim. */
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#endif
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rc = dc_inv_test(MEM_RAM);
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ret += rc;
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#ifdef UART
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print_n(rc + 0x9e8daa91);
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print_str("\n");
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#else
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report(rc + 0x9e8daa91);
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#endif
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#endif
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#ifdef UART
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print_str("IC test : ");
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#endif
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rc = ic_test();
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rc = ic_test();
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report(rc);
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ret += rc;
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#ifdef UART
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print_n(rc + 0xdeaddead);
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print_str("\n");
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#else
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report(rc + 0xdeaddead);
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#endif
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#ifndef OR1KSIM
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#ifdef UART
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print_str("IC invalidate test : ");
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#endif
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ic_enable();
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rc = ic_inv_test();
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ret += rc;
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#ifdef UART
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print_n(rc + 0xdeadde8f);
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print_str("\n");
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while(1);
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#else
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report(rc + 0xdeadde8f);
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#endif
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#endif
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report(ret + 0xdeaddca1);
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exit(0);
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exit(0);
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return 0;
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return 0;
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}
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}
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