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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [except.S] - Diff between revs 956 and 957

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Rev 956	Rev 957
Line 1...	Line 1...
`/* Support file for c based tests */`	`/* Support file for c based tests */`
`#include "spr_defs.h"`	`#include "spr_defs.h"`
	`#include "board.h"`

`#define reset _reset`	`#define reset _reset`

	`#define MC_CSR (0x00)`
	`#define MC_POC (0x04)`
	`#define MC_BA_MASK (0x08)`
	`#define MC_CSC(i) (0x10 + (i) * 8)`
	`#define MC_TMS(i) (0x14 + (i) * 8)`

`.section .stack`	`.section .stack`
`.space 0x1000`	`.space 0x1000`
`_stack:`	`_stack:`

`.section .except, "ax"`
`.extern _reset_support`	`.extern _reset_support`
`.extern _c_reset`	`.extern _c_reset`
`.extern _excpt_buserr`	`.extern _excpt_buserr`
`.extern _excpt_dpfault`	`.extern _excpt_dpfault`
`.extern _excpt_ipfault`	`.extern _excpt_ipfault`
Line 23...	Line 29...
`.extern _excpt_syscall`	`.extern _excpt_syscall`
`.extern _excpt_break`	`.extern _excpt_break`
`.extern _excpt_trap`	`.extern _excpt_trap`


`.org 0x100`	`.section .except, "ax"`
`_reset_vector:`
`l.nop`
`l.nop`
`l.addi r2,r0,0x0`
`l.addi r3,r0,0x0`
`l.addi r4,r0,0x0`
`l.addi r5,r0,0x0`
`l.addi r6,r0,0x0`
`l.addi r7,r0,0x0`
`l.addi r8,r0,0x0`
`l.addi r9,r0,0x0`
`l.addi r10,r0,0x0`
`l.addi r11,r0,0x0`
`l.addi r12,r0,0x0`
`l.addi r13,r0,0x0`
`l.addi r14,r0,0x0`
`l.addi r15,r0,0x0`
`l.addi r16,r0,0x0`
`l.addi r17,r0,0x0`
`l.addi r18,r0,0x0`
`l.addi r19,r0,0x0`
`l.addi r20,r0,0x0`
`l.addi r21,r0,0x0`
`l.addi r22,r0,0x0`
`l.addi r23,r0,0x0`
`l.addi r24,r0,0x0`
`l.addi r25,r0,0x0`
`l.addi r26,r0,0x0`
`l.addi r27,r0,0x0`
`l.addi r28,r0,0x0`
`l.addi r29,r0,0x0`
`l.addi r30,r0,0x0`
`l.addi r31,r0,0x0`

`l.movhi r1,hi(_stack)`
`l.ori r1,r1,lo(_stack)`

`/* Check if this is RTL version */`
`l.lbz r3,0(r0)`
`l.sfeqi r3,0xff`
`l.bf 2f`
`l.nop`
`l.movhi r3,hi(_src_beg)`
`l.ori r3,r3,lo(_src_beg)`
`l.movhi r4,hi(_dst_beg)`
`l.ori r4,r4,lo(_dst_beg)`
`l.movhi r5,hi(_dst_end)`
`l.ori r5,r5,lo(_dst_end)`
`l.sub r5,r5,r4`
`l.sfeqi r5,0`
`l.bf 2f`
`l.nop`
`1: l.lwz r6,0(r3)`
`l.sw 0(r4),r6`
`l.addi r3,r3,4`
`l.addi r4,r4,4`
`l.addi r5,r5,-4`
`l.sfgtsi r5,0`
`l.bf 1b`
`l.nop`

`2:`

`l.movhi r2,hi(reset)`
`l.ori r2,r2,lo(reset)`
`l.jr r2`
`l.nop`

`.org 0x200`
`_buserr_vector:`	`_buserr_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_buserr)`	`l.movhi r10,hi(_excpt_buserr)`
`l.ori r10,r10,lo(_excpt_buserr)`	`l.ori r10,r10,lo(_excpt_buserr)`
`l.lwz r10,0x0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_buserr_vector_end:`

`.org 0x300`
`_dpfault_vector:`	`_dpfault_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`/*`	`l.ori r9,r9,lo(store_regs)`
`l.mfspr r3,r0,SPR_EPCR_BASE`
`l.addi r3,r3,-4`
`l.mtspr r0,r3,SPR_EPCR_BASE`
`*/`
`l.movhi r9,hi(end_except)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_dpfault)`	`l.movhi r10,hi(_excpt_dpfault)`
`l.ori r10,r10,lo(_excpt_dpfault)`	`l.ori r10,r10,lo(_excpt_dpfault)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_dpfault_vector_end:`

`.org 0x400`
`_ipfault_vector:`	`_ipfault_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_ipfault)`	`l.movhi r10,hi(_excpt_ipfault)`
`l.ori r10,r10,lo(_excpt_ipfault)`	`l.ori r10,r10,lo(_excpt_ipfault)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_ipfault_vector_end:`

`.org 0x500`
`_lpint_vector:`	`_lpint_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_tick)`	`l.movhi r10,hi(_excpt_tick)`
`l.ori r10,r10,lo(_excpt_tick)`	`l.ori r10,r10,lo(_excpt_tick)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_lpint_vector_end:`

`.org 0x600`
`_align_vector:`	`_align_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_align)`	`l.movhi r10,hi(_excpt_align)`
`l.ori r10,r10,lo(_excpt_align)`	`l.ori r10,r10,lo(_excpt_align)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_align_vector_end:`

`.org 0x700`
`_illinsn_vector:`	`_illinsn_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_illinsn)`	`l.movhi r10,hi(_excpt_illinsn)`
`l.ori r10,r10,lo(_excpt_illinsn)`	`l.ori r10,r10,lo(_excpt_illinsn)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_illinsn_vector_end:`

`.org 0x800`
`_hpint_vector:`	`_hpint_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_int)`	`l.movhi r10,hi(_excpt_int)`
`l.ori r10,r10,lo(_excpt_int)`	`l.ori r10,r10,lo(_excpt_int)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_hpint_vector_end:`

`.org 0x900`
`_dtlbmiss_vector:`	`_dtlbmiss_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`/*`	`l.ori r9,r9,lo(store_regs)`
`l.mfspr r3,r0,SPR_EPCR_BASE`
`l.addi r3,r3,-4`
`l.mtspr r0,r3,SPR_EPCR_BASE`
`*/`
`l.movhi r9,hi(end_except)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_dtlbmiss)`	`l.movhi r10,hi(_excpt_dtlbmiss)`
`l.ori r10,r10,lo(_excpt_dtlbmiss)`	`l.ori r10,r10,lo(_excpt_dtlbmiss)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_dtlbmiss_vector_end:`

`.org 0xa00`
`_itlbmiss_vector:`	`_itlbmiss_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_itlbmiss)`	`l.movhi r10,hi(_excpt_itlbmiss)`
`l.ori r10,r10,lo(_excpt_itlbmiss)`	`l.ori r10,r10,lo(_excpt_itlbmiss)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_itlbmiss_vector_end:`

`.org 0xb00`
`_range_vector:`	`_range_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_range)`	`l.movhi r10,hi(_excpt_range)`
`l.ori r10,r10,lo(_excpt_range)`	`l.ori r10,r10,lo(_excpt_range)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_range_vector_end:`

`.org 0xc00`
`_syscall_vector:`	`_syscall_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_syscall)`	`l.movhi r10,hi(_excpt_syscall)`
`l.ori r10,r10,lo(_excpt_syscall)`	`l.ori r10,r10,lo(_excpt_syscall)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_syscall_vector_end:`

`.org 0xd00`
`_break_vector:`	`_break_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_break)`	`l.movhi r10,hi(_excpt_break)`
`l.ori r10,r10,lo(_excpt_break)`	`l.ori r10,r10,lo(_excpt_break)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`
`l.nop`	`l.nop`
	`_break_vector_end:`

`.org 0xe00`
`_trap_vector:`	`_trap_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.sw 0x1c(r1),r10`
`l.nop`	`l.movhi r9,hi(store_regs)`
`l.movhi r9,hi(end_except)`	`l.ori r9,r9,lo(store_regs)`
`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_trap)`	`l.movhi r10,hi(_excpt_trap)`
`l.ori r10,r10,lo(_excpt_trap)`	`l.ori r10,r10,lo(_excpt_trap)`
`l.lwz r10,0(r10)`	`l.jr r9`
`l.jr r10`	`l.nop`
	`_trap_vector_end:`

	`.section .text`

	`.org 0x100`
	`_reset_vector:`
	`l.addi r2,r0,0x0`
	`l.addi r3,r0,0x0`
	`l.addi r4,r0,0x0`
	`l.addi r5,r0,0x0`
	`l.addi r6,r0,0x0`
	`l.addi r7,r0,0x0`
	`l.addi r8,r0,0x0`
	`l.addi r9,r0,0x0`
	`l.addi r10,r0,0x0`
	`l.addi r11,r0,0x0`
	`l.addi r12,r0,0x0`
	`l.addi r13,r0,0x0`
	`l.addi r14,r0,0x0`
	`l.addi r15,r0,0x0`
	`l.addi r16,r0,0x0`
	`l.addi r17,r0,0x0`
	`l.addi r18,r0,0x0`
	`l.addi r19,r0,0x0`
	`l.addi r20,r0,0x0`
	`l.addi r21,r0,0x0`
	`l.addi r22,r0,0x0`
	`l.addi r23,r0,0x0`
	`l.addi r24,r0,0x0`
	`l.addi r25,r0,0x0`
	`l.addi r26,r0,0x0`
	`l.addi r27,r0,0x0`
	`l.addi r28,r0,0x0`
	`l.addi r29,r0,0x0`
	`l.addi r30,r0,0x0`
	`l.addi r31,r0,0x0`

	`l.movhi r3,hi(start)`
	`l.ori r3,r3,lo(start)`
	`l.jr r3`
	`l.nop`
	`start:`
	`l.jal _init_mc`
	`l.nop`

	`l.movhi r1,hi(_stack)`
	`l.ori r1,r1,lo(_stack)`

	`/* Setup exception wrappers */`
	`l.movhi r3,hi(_src_beg)`
	`l.ori r3,r3,lo(_src_beg)`
	`l.addi r7,r0,0x100`

	`1: l.addi r7,r7,0x100`
	`l.sfeqi r7,0xf00`
	`l.bf 1f`
	`l.nop`
	`l.addi r4,r7,0`
	`l.addi r5,r0,0`
	`2:`
	`l.lwz r6,0(r3)`
	`l.sw 0(r4),r6`
	`l.addi r3,r3,4`
	`l.addi r4,r4,4`
	`l.addi r5,r5,1`
	`l.sfeqi r5,9`
	`l.bf 1b`
	`l.nop`
	`l.j 2b`
	`l.nop`
	`1:`
	`/* Copy data section */`
	`l.movhi r4,hi(_dst_beg)`
	`l.ori r4,r4,lo(_dst_beg)`
	`l.movhi r5,hi(_dst_end)`
	`l.ori r5,r5,lo(_dst_end)`
	`l.sub r5,r5,r4`
	`l.sfeqi r5,0`
	`l.bf 2f`
	`l.nop`
	`1: l.lwz r6,0(r3)`
	`l.sw 0(r4),r6`
	`l.addi r3,r3,4`
	`l.addi r4,r4,4`
	`l.addi r5,r5,-4`
	`l.sfgtsi r5,0`
	`l.bf 1b`
	`l.nop`

	`2:`

	`l.movhi r2,hi(reset)`
	`l.ori r2,r2,lo(reset)`
	`l.jr r2`
	`l.nop`

	`_init_mc:`

	`l.movhi r3,hi(MC_BASE_ADDR)`
	`l.ori r3,r3,lo(MC_BASE_ADDR)`

	`l.addi r4,r3,MC_CSC(0)`
	`l.movhi r5,hi(FLASH_BASE_ADDR)`
	`l.srai r5,r5,5`
	`l.ori r5,r5,0x0025`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_TMS(0)`
	`l.movhi r5,hi(FLASH_TMS_VAL)`
	`l.ori r5,r5,lo(FLASH_TMS_VAL)`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_BA_MASK`
	`l.addi r5,r0,MC_MASK_VAL`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_CSR`
	`l.movhi r5,hi(MC_CSR_VAL)`
	`l.ori r5,r5,lo(MC_CSR_VAL)`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_TMS(1)`
	`l.movhi r5,hi(SDRAM_TMS_VAL)`
	`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_CSC(1)`
	`l.movhi r5,hi(SDRAM_BASE_ADDR)`
	`l.srai r5,r5,5`
	`l.ori r5,r5,0x0411`
	`l.sw 0(r4),r5`

	`l.jr r9`
`l.nop`	`l.nop`

`store_regs:`	`store_regs:`
`l.sw 0x00(r1),r3`	`l.sw 0x00(r1),r3`
`l.sw 0x04(r1),r4`	`l.sw 0x04(r1),r4`
`l.sw 0x08(r1),r5`	`l.sw 0x08(r1),r5`
`l.sw 0x0c(r1),r6`	`l.sw 0x0c(r1),r6`
`l.sw 0x10(r1),r7`	`l.sw 0x10(r1),r7`
`l.sw 0x14(r1),r8`	`l.sw 0x14(r1),r8`
`l.sw 0x1c(r1),r10`
`l.sw 0x20(r1),r11`	`l.sw 0x20(r1),r11`
`l.sw 0x24(r1),r12`	`l.sw 0x24(r1),r12`
`l.sw 0x28(r1),r13`	`l.sw 0x28(r1),r13`
`l.sw 0x2c(r1),r14`	`l.sw 0x2c(r1),r14`
`l.sw 0x30(r1),r15`	`l.sw 0x30(r1),r15`
Line 313...	Line 347...
`l.sw 0x60(r1),r27`	`l.sw 0x60(r1),r27`
`l.sw 0x64(r1),r28`	`l.sw 0x64(r1),r28`
`l.sw 0x68(r1),r29`	`l.sw 0x68(r1),r29`
`l.sw 0x6c(r1),r30`	`l.sw 0x6c(r1),r30`
`l.sw 0x70(r1),r31`	`l.sw 0x70(r1),r31`
`l.jr r9`	`l.movhi r9,hi(end_except)`
	`l.ori r9,r9,lo(end_except)`
	`l.lwz r10,0(r10)`
	`l.jr r10`
`l.nop`	`l.nop`

`end_except:`	`end_except:`
`l.lwz r3,0x00(r1)`	`l.lwz r3,0x00(r1)`
`l.lwz r4,0x04(r1)`	`l.lwz r4,0x04(r1)`

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