| Line 373... |
Line 373... |
ret = call ((unsigned long)&int_trigger, 0);
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ret = call ((unsigned long)&int_trigger, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_HPINT));
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ASSERT(except_mask == (1 << V_HPINT));
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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ASSERT(except_ea == 0);
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#if 0
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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| Line 391... |
Line 391... |
ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_LPINT));
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ASSERT(except_mask == (1 << V_LPINT));
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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ASSERT(except_ea == 0);
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ASSERT(except_ea == 0);
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#endif
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 454... |
Line 455... |
/* Check if there was ITLB miss exception */
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/* Check if there was ITLB miss exception */
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ret = call (ea, 0);
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ret = call (ea, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_pc == ea);
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ASSERT(except_pc == ea);
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ASSERT(except_ea == ea);
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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| Line 471... |
Line 471... |
/* Check if there was IPF miss exception */
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/* Check if there was IPF miss exception */
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ret = call (ea, 0);
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ret = call (ea, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_IPF));
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ASSERT(except_mask == (1 << V_IPF));
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ASSERT(except_pc == ea);
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ASSERT(except_pc == ea);
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ASSERT(except_ea == ea);
|
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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itlb_val = SPR_ITLBTR_CI;
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itlb_val = SPR_ITLBTR_CI;
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|
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| Line 488... |
Line 487... |
/* Check if there was ITLB miss exception */
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/* Check if there was ITLB miss exception */
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ret = call (ea, 0);
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ret = call (ea, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_pc == ea + 4);
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ASSERT(except_pc == ea + 4);
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ASSERT(except_ea == ea + 8);
|
|
ASSERT(ret == 0);
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ASSERT(ret == 0);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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|
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| Line 505... |
Line 503... |
/* Check if there was IPF exception */
|
/* Check if there was IPF exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_pc == ea + 4);
|
ASSERT(except_pc == ea + 4);
|
ASSERT(except_ea == ea + 8);
|
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
| Line 747... |
Line 744... |
/* Check if there was illegal insn exception */
|
/* Check if there was illegal insn exception */
|
ret = call (RAM_START + 4, 0 );
|
ret = call (RAM_START + 4, 0 );
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_pc == RAM_START + 4);
|
ASSERT(except_pc == RAM_START + 4);
|
ASSERT(except_ea == RAM_START + 4);
|
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
| Line 760... |
Line 756... |
/* Check if there was illegal insn exception */
|
/* Check if there was illegal insn exception */
|
ret = call (RAM_START, 0 );
|
ret = call (RAM_START, 0 );
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_pc == RAM_START);
|
ASSERT(except_pc == RAM_START);
|
ASSERT(except_ea == RAM_START + 4);
|
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Align test */
|
/* Align test */
|
| Line 1116... |
Line 1111... |
|
|
int main (void)
|
int main (void)
|
{
|
{
|
int ret;
|
int ret;
|
|
|
|
printf("except_test\n");
|
|
|
/* Register bus error handler */
|
/* Register bus error handler */
|
excpt_buserr = (unsigned long)bus_err_handler;
|
excpt_buserr = (unsigned long)bus_err_handler;
|
|
|
/* Register illegal insn handler */
|
/* Register illegal insn handler */
|
excpt_illinsn = (unsigned long)ill_insn_handler;
|
excpt_illinsn = (unsigned long)ill_insn_handler;
|
| Line 1175... |
Line 1172... |
|
|
/* Trap test */
|
/* Trap test */
|
trap_test ();
|
trap_test ();
|
|
|
/* Range test */
|
/* Range test */
|
range_test ();
|
// range_test ();
|
|
|
/* Exception priority test */
|
/* Exception priority test */
|
except_priority_test ();
|
except_priority_test ();
|
|
|
report (0xdeaddead);
|
report (0xdeaddead);
|
