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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [int_test.S] - Diff between revs 576 and 600

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Rev 576 Rev 600
Line 23... Line 23...
.section .except
.section .except
.org 0x100
.org 0x100
  l.j     _main
  l.j     _main
  l.nop
  l.nop
 
 
.org 0x800
.org 0x500
#
#
# Interrupt handler
# Tick timer exception handler
#
#
 
 
  l.addi  r31,r3,0
  l.addi  r31,r3,0
# get interrupted program pc
# get interrupted program pc
  l.mfspr r25,r0,SPR_EPCR_BASE
  l.mfspr r25,r0,SPR_EPCR_BASE
Line 89... Line 89...
  l.nop
  l.nop
 
 
.section  .text
.section  .text
_main:
_main:
        l.nop
        l.nop
 
  l.addi  r3,r0,SPR_SR_SM
 
  l.mtspr r0,r3,SPR_SR
        l.nop
        l.nop
 
 
#
#
# set tick counter to initial 3 cycles
# set tick counter to initial 3 cycles
#
#
Line 110... Line 112...
#
#
        l.movhi r5,0xffff
        l.movhi r5,0xffff
        l.ori   r5,r5,0xffff
        l.ori   r5,r5,0xffff
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
 
 
# Set r20 to hold enable exceptions and interrupts
# Set r20 to hold enable tick exception
        l.mfspr r20,r0,SPR_SR
        l.mfspr r20,r0,SPR_SR
        l.ori r20,r20,SPR_SR_SUPV|SPR_SR_EXR|SPR_SR_EIR|SPR_SR_F
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
 
 
# Set r21 to hold value of TTMR
# Set r21 to hold value of TTMR
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
        l.add  r21,r5,r17
        l.add  r21,r5,r17
 
 
Line 307... Line 309...
  l.j     _ok
  l.j     _ok
  l.nop
  l.nop
 
 
_resume:
_resume:
  l.mfspr  r27,r0,SPR_ESR_BASE
  l.mfspr  r27,r0,SPR_ESR_BASE
  l.addi   r26,r0,SPR_SR_EIR
  l.addi   r26,r0,SPR_SR_TEE
  l.addi   r28,r0,-1
  l.addi   r28,r0,-1
  l.xor    r26,r26,r28
  l.xor    r26,r26,r28
  l.and    r26,r26,r27
  l.and    r26,r26,r27
  l.mtspr  r0,r26,SPR_ESR_BASE
  l.mtspr  r0,r26,SPR_ESR_BASE
 
 

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