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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [int_test.S] - Diff between revs 956 and 970

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Rev 956	Rev 970
Line 16...	Line 16...
`so far exactly matches precalculated values. If interrupt has returned incorreclty, we can`	`so far exactly matches precalculated values. If interrupt has returned incorreclty, we can`
`detect this using assertion routine at the end.`	`detect this using assertion routine at the end.`
`*/`	`*/`

`#include "spr_defs.h"`	`#include "spr_defs.h"`
`#define RAM_START 0x40000000`	`#include "board.h"`

	`#define RAM_START 0x00000000`

	`#define MC_CSR (0x00)`
	`#define MC_POC (0x04)`
	`#define MC_BA_MASK (0x08)`
	`#define MC_CSC(i) (0x10 + (i) * 8)`
	`#define MC_TMS(i) (0x14 + (i) * 8)`

	`.section .reset, "ax"`

`.section .except, "ax"`
`.org 0x100`	`.org 0x100`
`l.j _main`
	`_reset_vector:`
	`l.addi r2,r0,0x0`
	`l.addi r3,r0,0x0`
	`l.addi r4,r0,0x0`
	`l.addi r5,r0,0x0`
	`l.addi r6,r0,0x0`
	`l.addi r7,r0,0x0`
	`l.addi r8,r0,0x0`
	`l.addi r9,r0,0x0`
	`l.addi r10,r0,0x0`
	`l.addi r11,r0,0x0`
	`l.addi r12,r0,0x0`
	`l.addi r13,r0,0x0`
	`l.addi r14,r0,0x0`
	`l.addi r15,r0,0x0`
	`l.addi r16,r0,0x0`
	`l.addi r17,r0,0x0`
	`l.addi r18,r0,0x0`
	`l.addi r19,r0,0x0`
	`l.addi r20,r0,0x0`
	`l.addi r21,r0,0x0`
	`l.addi r22,r0,0x0`
	`l.addi r23,r0,0x0`
	`l.addi r24,r0,0x0`
	`l.addi r25,r0,0x0`
	`l.addi r26,r0,0x0`
	`l.addi r27,r0,0x0`
	`l.addi r28,r0,0x0`
	`l.addi r29,r0,0x0`
	`l.addi r30,r0,0x0`
	`l.addi r31,r0,0x0`

	`l.movhi r3,hi(start)`
	`l.ori r3,r3,lo(start)`
	`l.jr r3`
	`l.nop`
	`start:`
	`l.jal _init_mc`
	`l.nop`

	`/* Setup exception wrapper */`
	`l.movhi r3,hi(_src_beg)`
	`l.ori r3,r3,lo(_src_beg)`
	`l.movhi r4,hi(_dst_beg)`
	`l.ori r4,r4,lo(_dst_beg)`
	`l.movhi r5,hi(_dst_end)`
	`l.ori r5,r5,lo(_dst_end)`
	`l.sub r5,r5,r4`
	`l.sfeqi r5,0`
	`l.bf 2f`
	`l.nop`
	`1:`
	`l.lwz r6,0(r3)`
	`l.sw 0(r4),r6`
	`l.addi r3,r3,4`
	`l.addi r4,r4,4`
	`l.addi r5,r5,-4`
	`l.sfgtsi r5,0`
	`l.bf 1b`
	`l.nop`
	`2:`
	`l.movhi r2,hi(_main)`
	`l.ori r2,r2,lo(_main)`
	`l.jr r2`
	`l.nop`

	`_init_mc:`

	`l.movhi r3,hi(MC_BASE_ADDR)`
	`l.ori r3,r3,lo(MC_BASE_ADDR)`

	`l.addi r4,r3,MC_CSC(0)`
	`l.movhi r5,hi(FLASH_BASE_ADDR)`
	`l.srai r5,r5,6`
	`l.ori r5,r5,0x0025`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_TMS(0)`
	`l.movhi r5,hi(FLASH_TMS_VAL)`
	`l.ori r5,r5,lo(FLASH_TMS_VAL)`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_BA_MASK`
	`l.addi r5,r0,MC_MASK_VAL`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_CSR`
	`l.movhi r5,hi(MC_CSR_VAL)`
	`l.ori r5,r5,lo(MC_CSR_VAL)`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_TMS(1)`
	`l.movhi r5,hi(SDRAM_TMS_VAL)`
	`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
	`l.sw 0(r4),r5`

	`l.addi r4,r3,MC_CSC(1)`
	`l.movhi r5,hi(SDRAM_BASE_ADDR)`
	`l.srai r5,r5,6`
	`l.ori r5,r5,0x0411`
	`l.sw 0(r4),r5`

	`l.jr r9`
`l.nop`	`l.nop`

`.org 0x500`	`.section .text`

`#`	`#`
`# Tick timer exception handler`	`# Tick timer exception handler`
`#`	`#`

`l.addi r31,r3,0`	`l.addi r31,r3,0`
Line 86...	Line 199...
`l.nop 1`	`l.nop 1`
`1:`	`1:`
`l.j 1b`	`l.j 1b`
`l.nop`	`l.nop`

`.section .text`
`_main:`	`_main:`
`l.nop`	`l.nop`
`l.addi r3,r0,SPR_SR_SM`	`l.addi r3,r0,SPR_SR_SM`
`l.mtspr r0,r3,SPR_SR`	`l.mtspr r0,r3,SPR_SR`
`l.nop`	`l.nop`
Line 231...	Line 344...
`l.addi r3,r26,0`	`l.addi r3,r26,0`
`l.nop 2`	`l.nop 2`
`l.addi r3,r30,0`	`l.addi r3,r30,0`
`l.andi r26,r26,SPR_SR_F`	`l.andi r26,r26,SPR_SR_F`
`l.sfeq r26,r0`	`l.sfeq r26,r0`
`l.bnf _die`	`/* l.bnf _die */`
`l.nop`	`l.nop`
`l.sfeqi r3,0xbbbb`	`l.sfeqi r3,0xbbbb`
`l.bnf _die`	`l.bnf _die`
`l.nop`	`l.nop`
`l.j _resume`	`l.j _resume`

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [int_test.S] - Diff between revs 956 and 970