| Line 32... |
Line 32... |
#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
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#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
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#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
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#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
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#define TLB_CODE_MASK 0xfffff000
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#define TLB_CODE_MASK 0xfffff000
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#define TLB_PR_MASK 0x00000fff
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#define TLB_PR_MASK 0x00000fff
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#define TLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \
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SPR_DTLBTR_URE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SWE )
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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/* Extern functions */
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/* Extern functions */
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extern void lo_dmmu_en (void);
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extern void lo_dmmu_en (void);
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extern void lo_immu_en (void);
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extern void lo_immu_en (void);
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| Line 46... |
Line 54... |
unsigned long dtlb_val;
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unsigned long dtlb_val;
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/* ITLB mode status */
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/* ITLB mode status */
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unsigned long itlb_val;
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unsigned long itlb_val;
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/* DTLB miss counter */
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int dtlb_miss_count;
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/* ITLB miss counter */
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int itlb_miss_count;
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/* EA of last DTLB miss exception */
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unsigned long dtlb_miss_ea;
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/* EA of last ITLB miss exception */
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unsigned long itlb_miss_ea;
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/*inline static
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/*inline static
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unsigned int dtlb_write_entry (int way, int entry, unsigned int val)
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unsigned int dtlb_write_entry (int way, int entry, unsigned int val)
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{
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{
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mtspr (SPR_DTLBMR_BASE(way) + entry, val);
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mtspr (SPR_DTLBMR_BASE(way) + entry, val);
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}
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}
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*/
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*/
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void fail (char *func, int line)
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{
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#ifndef __FUNCTION__
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#define __FUNCTION__ "?"
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#endif
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printf ("Test failed in %s:%i\n", func, line);
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report(0xeeeeeeee);
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exit (1);
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}
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/* DTLB miss exception handler */
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/* DTLB miss exception handler */
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void dtlb_miss_handler (void)
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void dtlb_miss_handler (void)
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{
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{
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unsigned long ea, ta, tlbtr;
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unsigned long ea, ta, tlbtr;
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int set, way = 0;
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int set, way = 0;
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int i;
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int i;
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/* Get EA that cause the exception */
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/* Get EA that cause the exception */
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ea = mfspr (SPR_EEAR_BASE);
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ea = mfspr (SPR_EEAR_BASE);
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printf("ea = %.8lx\n", ea);
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/* Find TLB set and LRU way */
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/* Find TLB set and LRU way */
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set = (ea / PAGE_SIZE) % DTLB_SETS;
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set = (ea / PAGE_SIZE) % DTLB_SETS;
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for (i = 0; i < DTLB_WAYS; i++) {
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for (i = 0; i < DTLB_WAYS; i++) {
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if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {
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if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {
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way = i;
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way = i;
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break;
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break;
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}
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}
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}
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}
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printf("set = %.8lx\n", set);
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printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
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if (RAM_START < ea < CODE_END_ADD) {
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printf("RAM_START< ea < CODE_END_ADD\n", ea);
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if ((RAM_START <= ea) && (ea < CODE_END_ADD)) {
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/* If this is acces to data of this program set one to one translation */
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/* If this is acces to data of this program set one to one translation */
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | SPR_DTLBTR_CI | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | SPR_DTLBTR_SWE);
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mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | TLB_PR_NOLIMIT);
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return;
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return;
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}
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}
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/* Update DTLB miss counter and EA */
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dtlb_miss_count++;
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dtlb_miss_ea = ea;
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/* Whatever access is in progress, translated address have to point to physical RAM */
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/* Whatever access is in progress, translated address have to point to physical RAM */
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ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START;
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ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2);
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printf("ta = %.8lx\n", ta);
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/* Set appropriate TLB entry */
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/* Set appropriate TLB entry */
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switch (dtlb_val & TLB_CODE_MASK) {
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switch (dtlb_val & TLB_CODE_MASK) {
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case TLB_CODE_ONE_TO_ONE:
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case TLB_CODE_ONE_TO_ONE:
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tlbtr = (ta & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK);
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tlbtr = (ta & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
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printf("1: tlbtr = %.8lx\n", tlbtr);
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break;
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break;
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case TLB_CODE_PLUS_ONE_PAGE:
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case TLB_CODE_PLUS_ONE_PAGE:
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if ((ta + PAGE_SIZE) >= (RAM_START + RAM_SIZE))
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if ((ta + PAGE_SIZE) >= (RAM_START + RAM_SIZE))
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/* Wrapp last page */
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/* Wrapp last page */
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tlbtr = (((ta & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2)) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK);
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tlbtr = (((ta & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2)) & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
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else
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else
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tlbtr = ((ta + PAGE_SIZE) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK);
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tlbtr = ((ta + PAGE_SIZE) & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
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printf("2: tlbtr = %.8lx\n", tlbtr);
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break;
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break;
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case TLB_CODE_MINUS_ONE_PAGE:
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case TLB_CODE_MINUS_ONE_PAGE:
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if ((ta - PAGE_SIZE) < (RAM_START + (RAM_SIZE/2)))
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if ((ta - PAGE_SIZE) < (RAM_START + (RAM_SIZE/2)))
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/* Wrapp first page */
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/* Wrapp first page */
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tlbtr = ((ta - PAGE_SIZE + (RAM_SIZE/2)) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK);
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tlbtr = ((ta - PAGE_SIZE + (RAM_SIZE/2)) & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
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else
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else
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tlbtr = ((ta - PAGE_SIZE) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK);
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tlbtr = ((ta - PAGE_SIZE) & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
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printf("3: tlbtr = %.8lx\n", tlbtr);
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break;
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break;
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}
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}
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/* Set DTLB entry */
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/* Set DTLB entry */
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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| Line 171... |
Line 208... |
add += PAGE_SIZE;
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add += PAGE_SIZE;
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}
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}
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}
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}
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/* Valid bit test
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Set all ways of one set to be invalid, perform
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access so miss handler will set them to valid,
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try access again - there should be no miss exceptions */
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int dtlb_valid_bit_test (int set)
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{
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int i;
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/* Reset DTLB miss counter and EA */
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dtlb_miss_count = 0;
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dtlb_miss_ea = 0;
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/* Set dtlb permisions */
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dtlb_val = TLB_PR_NOLIMIT;
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/* Resetv DTLBMR for every way */
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for (i = 0; i < DTLB_WAYS; i++) {
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mtspr (SPR_DTLBMR_BASE(i) + set, 0);
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}
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/* Perform writes to address, that is not in DTLB */
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for (i = 0; i < DTLB_WAYS; i++) {
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REG32(RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)) = i;
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/* Check if there was DTLB miss */
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ASSERT(dtlb_miss_count == (i + 1));
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ASSERT(dtlb_miss_ea == (RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
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}
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/* Reset DTLB miss counter and EA */
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dtlb_miss_count = 0;
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dtlb_miss_ea = 0;
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/* Perform reads to address, that is now in DTLB */
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for (i = 0; i < DTLB_WAYS; i++) {
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ASSERT(REG32(RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)) == i);
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/* Check if there was DTLB miss */
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ASSERT(dtlb_miss_count == 0);
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}
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/* Reset valid bits */
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for (i = 0; i < DTLB_WAYS; i++) {
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mtspr (SPR_DTLBMR_BASE(i) + set, mfspr (SPR_DTLBMR_BASE(i) + set) & ~SPR_DTLBMR_V);
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}
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/* Perform reads to address, that is now in DTLB but is invalid */
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for (i = 0; i < DTLB_WAYS; i++) {
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ASSERT(REG32(RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)) == i);
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/* Check if there was DTLB miss */
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ASSERT(dtlb_miss_count == (i + 1));
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ASSERT(dtlb_miss_ea == (RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
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}
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return 0;
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}
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int main (void)
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int main (void)
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{
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{
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int i;
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dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | SPR_DTLBTR_SWE;
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/* Enable DMMU */
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/* Enable DMMU */
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dmmu_enable();
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dmmu_enable();
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/* Valid bit testing */
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for (i = 0; i < 15; i++)
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dtlb_valid_bit_test (DTLB_SETS - i - 1);
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/* Write pattern */
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/* Write pattern */
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write_pattern(0x40000000, 0x40100000);
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// write_pattern(0x40000000, 0x40100000);
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/* Enable IMMU */
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/* Enable IMMU */
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// immu_enable();
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// immu_enable();
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exit(0);
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exit(0);
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