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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [uos/] [spr_defs.h] - Diff between revs 222 and 600

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Line 41... Line 41... 
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
 
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
 
 
 
 
 
/* System control and status group */
 
/* System control and status group */
 
#define SPR_VR          (SPRGROUP_SYS + 0)
 
#define SPR_VR          (SPRGROUP_SYS + 0)
 
#define SPR_UPR         (SPRGROUP_SYS + 1)
 
#define SPR_UPR         (SPRGROUP_SYS + 1)
 
#define SPR_PC          (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
 
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
 
 
 
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
 
 
 
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
 
 
 
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
 
 
 
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
 
 
 
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
 
 
 
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
 
 
 
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
 
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
 
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
 
 
 
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
 
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
 
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
 
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
 
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
 
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
 
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
 
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
 
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
 
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
 
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
Line 95... Line 103... 
#define SPR_DMR2        (SPRGROUP_D + 17)
 
#define SPR_DMR2        (SPRGROUP_D + 17)
 
#define SPR_DWCR0       (SPRGROUP_D + 18)
 
#define SPR_DWCR0       (SPRGROUP_D + 18)
 
#define SPR_DWCR1       (SPRGROUP_D + 19)
 
#define SPR_DWCR1       (SPRGROUP_D + 19)
 
#define SPR_DSR         (SPRGROUP_D + 20)
 
#define SPR_DSR         (SPRGROUP_D + 20)
 
#define SPR_DRR         (SPRGROUP_D + 21)
 
#define SPR_DRR         (SPRGROUP_D + 21)
 
#define SPR_DIR         (SPRGROUP_D + 22)
 
 
 
 
 
 
 
/* Performance counters group */
 
/* Performance counters group */
 
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
 
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
 
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
 
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
 
 
 
 
Line 149... Line 156... 
/*
 
/*
 
 * Bit definitions for the Supervision Register
 
 * Bit definitions for the Supervision Register
 
 *
 
 *
 
 */
 
 */
 
#define SPR_SR_CID      0xf0000000  /* Context ID */
 
#define SPR_SR_CID      0xf0000000  /* Context ID */
 
#define SPR_SR_PXR      0x00008000  /* Partial exception recognition */
 
#define SPR_SR_FO       0x00008000  /* Fixed one */
 
#define SPR_SR_EP       0x00004000  /* Exception Prefix */
 
#define SPR_SR_EPH      0x00004000  /* Exception Prefixi High */
 
#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */
 
#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */
 
#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */
 
#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */
 
#define SPR_SR_OV       0x00000800  /* Overflow flag */
 
#define SPR_SR_OV       0x00000800  /* Overflow flag */
 
#define SPR_SR_CY       0x00000400  /* Carry flag */
 
#define SPR_SR_CY       0x00000400  /* Carry flag */
 
#define SPR_SR_F        0x00000200  /* Condition Flag */
 
#define SPR_SR_F        0x00000200  /* Condition Flag */
Line 162... Line 169... 
#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */
 
#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */
 
#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */
 
#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */
 
#define SPR_SR_DME      0x00000020  /* Data MMU Enable */
 
#define SPR_SR_DME      0x00000020  /* Data MMU Enable */
 
#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */
 
#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */
 
#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */
 
#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */
 
#define SPR_SR_EIR      0x00000004  /* External Interrupt Recognition */
 
#define SPR_SR_IEE      0x00000004  /* Interrupt Exception Enable */
 
#define SPR_SR_EXR      0x00000002  /* Exception Recognition */
 
#define SPR_SR_TEE      0x00000002  /* Tick timer Exception Enable */
 
#define SPR_SR_SUPV     0x00000001  /* Supervisor mode */
 
#define SPR_SR_SM       0x00000001  /* Supervisor Mode */
 
 
 
 
 
/*
 
/*
 
 * Bit definitions for the Data MMU Control Register
 
 * Bit definitions for the Data MMU Control Register
 
 *
 
 *
 
 */
 
 */
Line 230... Line 237... 
#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */
 
#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */
 
#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */
 
#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */
 
#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
 
#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
 
#define SPR_ITLBTR_A    0x00000010  /* Accessed */
 
#define SPR_ITLBTR_A    0x00000010  /* Accessed */
 
#define SPR_ITLBTR_D    0x00000020  /* Dirty */
 
#define SPR_ITLBTR_D    0x00000020  /* Dirty */
 
#define SPR_ITLBTR_URE  0x00000040  /* User Read Enable */
 
#define SPR_ITLBTR_SXE  0x00000040  /* User Read Enable */
 
#define SPR_ITLBTR_UWE  0x00000080  /* User Write Enable */
 
#define SPR_ITLBTR_UXE  0x00000080  /* User Write Enable */
 
#define SPR_ITLBTR_SRE  0x00000100  /* Supervisor Read Enable */
 
 
 
#define SPR_ITLBTR_SWE  0x00000200  /* Supervisor Write Enable (not used actually) */
 
 
 
#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */
 
#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */
 
 
 
 
 
/*
 
/*
 
 * Bit definitions for Data Cache Control register
 
 * Bit definitions for Data Cache Control register
 
 *
 
 *
Line 257... Line 262... 
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
 
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
 
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
 
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
 
#define SPR_DCR_SC      0x00000010  /* Signed compare */
 
#define SPR_DCR_SC      0x00000010  /* Signed compare */
 
#define SPR_DCR_CT      0x000000e0  /* Compare to */
 
#define SPR_DCR_CT      0x000000e0  /* Compare to */
 
 
 
 
 
 
 
/* Bit results with SPR_DCR_CC mask */
 
 
 
#define SPR_DCR_CC_MASKED 0x00000000
 
 
 
#define SPR_DCR_CC_EQUAL  0x00000001
 
 
 
#define SPR_DCR_CC_LESS   0x00000002
 
 
 
#define SPR_DCR_CC_LESSE  0x00000003
 
 
 
#define SPR_DCR_CC_GREAT  0x00000004
 
 
 
#define SPR_DCR_CC_GREATE 0x00000005
 
 
 
#define SPR_DCR_CC_NEQUAL 0x00000006
 
 
 
 
 
 
 
/* Bit results with SPR_DCR_CT mask */
 
 
 
#define SPR_DCR_CT_DISABLED 0x00000000
 
 
 
#define SPR_DCR_CT_IFEA     0x00000020
 
 
 
#define SPR_DCR_CT_LEA      0x00000040
 
 
 
#define SPR_DCR_CT_SEA      0x00000060
 
 
 
#define SPR_DCR_CT_LD       0x00000080
 
 
 
#define SPR_DCR_CT_SD       0x000000a0
 
 
 
#define SPR_DCR_CT_LSEA     0x000000c0
 
 
 
 
 
/*
 
/*
 
 * Bit definitions for Debug Mode 1 register
 
 * Bit definitions for Debug Mode 1 register
 
 *
 
 *
 
 */
 
 */
 
#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */
 
#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */
Line 300... Line 323... 
 */
 
 */
 
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
 
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
 
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
 
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
 
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
 
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
 
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
 
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
 
#define SPR_DSR_LPINTE  0x00000010  /* Low priority interrupt exception */
 
#define SPR_DSR_TTE     0x00000010  /* iTick Timer exception */
 
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
 
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
 
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
 
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
 
#define SPR_DSR_HPINTE  0x00000080  /* High priority interrupt exception */
 
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
 
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
 
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
 
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
 
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
 
#define SPR_DSR_RE      0x00000400  /* Range exception */
 
#define SPR_DSR_RE      0x00000400  /* Range exception */
 
#define SPR_DSR_SCE     0x00000800  /* System call exception */
 
#define SPR_DSR_SCE     0x00000800  /* System call exception */
 
#define SPR_DSR_BE      0x00001000  /* Breakpoint exception */
 
#define SPR_DSR_SSE     0x00001000  /* Single Step Exception */
 
 
 
#define SPR_DSR_TE      0x00002000  /* Trap exception */
 
 
 
 
 
/*
 
/*
 
 * Bit definitions for Debug reason register
 
 * Bit definitions for Debug reason register
 
 *
 
 *
 
 */
 
 */
 
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
 
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
 
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
 
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
 
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
 
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
 
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
 
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
 
#define SPR_DRR_LPINTE  0x00000010  /* Low priority interrupt exception */
 
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
 
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
 
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
 
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
 
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
 
#define SPR_DRR_HPINTE  0x00000080  /* High priority interrupt exception */
 
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
 
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
 
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
 
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
 
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
 
#define SPR_DRR_RE      0x00000400  /* Range exception */
 
#define SPR_DRR_RE      0x00000400  /* Range exception */
 
#define SPR_DRR_SCE     0x00000800  /* System call exception */
 
#define SPR_DRR_SCE     0x00000800  /* System call exception */
 
#define SPR_DRR_BE      0x00001000  /* Breakpoint exception */
 
#define SPR_DRR_TE      0x00001000  /* Trap exception */
 
 
 
 
 
/*
 
/*
 
 * Bit definitions for Performance counters mode registers
 
 * Bit definitions for Performance counters mode registers
 
 *
 
 *
 
 */
 
 */
Line 353... Line 377... 
 
 
 
 
/*
 
/*
 
 * Bit definitions for the Power management register
 
 * Bit definitions for the Power management register
 
 *
 
 *
 
 */
 
 */
 
#define SPR_PMR_SDF     0x00000001  /* Slow down factor */
 
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
 
#define SPR_PMR_DME     0x00000002  /* Doze mode enable */
 
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
 
#define SPR_PMR_SME     0x00000004  /* Sleep mode enable */
 
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
 
#define SPR_PMR_DCGE    0x00000008  /* Dynamic clock gating enable */
 
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
 
#define SPR_PMR_SUME    0x00000010  /* Suspend mode enable */
 
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
 
 
 
 
 
/*
 
/*
 
 * Bit definitions for PICMR
 
 * Bit definitions for PICMR
 
 *
 
 *
 
 */
 
 */
Line 385... Line 409... 
 */
 
 */
 
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
 
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
 
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
 
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
 
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
 
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
 
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
 
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
 
#define SPR_TTMR_CR     0x40000000  /* Continuous Run */
 
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
 
#define SPR_TTMR_TTE    0x80000000  /* Tick Timer Enable */
 
#define SPR_TTMR_SR     0x80000000  /* Single run */
 
 
 
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
 
 
 
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
 
 
 
 
 
 
 
/*
 
 
 
 * l.nop constants
 
 
 
 *
 
 
 
 */
 
 
 
#define NOP_NOP         0x0000      /* Normal nop instruction */
 
 
 
#define NOP_EXIT        0x0001      /* End of simulation */
 
 
 
#define NOP_REPORT      0x0002      /* Simple report */
 
 
 
#define NOP_PRINTF      0x0003      /* Simprintf instruction */
 
 
 
#define NOP_REPORT_FIRST 0x0400     /* Report with number */
 
 
 
#define NOP_REPORT_LAST 0x03ff      /* Report with number */
 
 
 
 
 
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