URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 499 |
Rev 600 |
| Line 1... |
Line 1... |
/* This file is part of test microkernel for OpenRISC 1000. */
|
/* This file is part of test microkernel for OpenRISC 1000. */
|
/* (C) 2001 Simon Srot, srot@opencores.org */
|
/* (C) 2001 Simon Srot, srot@opencores.org */
|
|
|
#include "spr_defs.h"
|
#include "spr_defs.h"
|
#include "int.h"
|
|
#include "support.h"
|
#include "support.h"
|
|
|
/* Tick timer period */
|
/* Tick timer period */
|
unsigned long tick_period;
|
unsigned long tick_period;
|
|
|
| Line 16... |
Line 15... |
{
|
{
|
/* Call inf routine */
|
/* Call inf routine */
|
(*tick_inf)();
|
(*tick_inf)();
|
|
|
/* Set new counter period iand clear inet pending bit */
|
/* Set new counter period iand clear inet pending bit */
|
/* mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_SR | (period & SPR_TTMR_PERIOD));*/
|
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (tick_period & SPR_TTMR_PERIOD));
|
}
|
}
|
|
|
/* Initialize routine */
|
/* Initialize routine */
|
int tick_init(unsigned long period, void (* inf)())
|
int tick_init(unsigned long period, void (* inf)())
|
{
|
{
|
/* Save tick timer period and inform routine */
|
/* Save tick timer period and inform routine */
|
tick_period = period;
|
tick_period = period;
|
tick_inf = inf;
|
tick_inf = inf;
|
|
|
/* Add interrupt handler */
|
|
int_add(V_TICK, tick_int, 0, INT_HIGH_PRI);
|
|
|
|
/* Set counter period, enable timer and interrupt */
|
/* Set counter period, enable timer and interrupt */
|
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_CR | (period & SPR_TTMR_PERIOD));
|
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD));
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.