URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_49/] [or1ksim/] [cache/] [dcache_model.c] - Diff between revs 1386 and 1402

Rev 1386	Rev 1402
Line 320...	Line 320...
`dc[set].way[way].tagaddr = -1;`	`dc[set].way[way].tagaddr = -1;`
`dc[set].way[way].lru = 0;`	`dc[set].way[way].lru = 0;`
`}`	`}`
`}`	`}`

`void dc_clock()`
`{`
`oraddr_t addr;`

`if ((addr = mfspr(SPR_DCBPR))) {`
`dc_simulate_read(addr, 4);`
`mtspr(SPR_DCBPR, 0);`
`}`
`if ((addr = mfspr(SPR_DCBFR)) != -1) {`
`dc_inv(addr);`
`mtspr(SPR_DCBFR, -1);`
`}`
`if ((addr = mfspr(SPR_DCBIR))) {`
`dc_inv(addr);`
`mtspr(SPR_DCBIR, 0);`
`}`
`if ((addr = mfspr(SPR_DCBWR))) {`
`mtspr(SPR_DCBWR, 0);`
`}`
`if ((addr = mfspr(SPR_DCBLR))) {`
`mtspr(SPR_DCBLR, 0);`
`}`
`}`

`/-----------------------------------------------------[ DC configuration ]---/`	`/-----------------------------------------------------[ DC configuration ]---/`
`void dc_enabled(union param_val val, void *dat)`	`void dc_enabled(union param_val val, void *dat)`
`{`	`{`
`config.dc.enabled = val.int_val;`	`config.dc.enabled = val.int_val;`
`setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0);`	`setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0);`