| Line 298... |
Line 298... |
if (config.bp.btic_sim) {
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if (config.bp.btic_sim) {
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printf("BTIC: hit %d(%d%%), miss %d\n", mstats.btic.hit, (mstats.btic.hit * 100) / SD(mstats.btic.hit + mstats.btic.miss), mstats.btic.miss);
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printf("BTIC: hit %d(%d%%), miss %d\n", mstats.btic.hit, (mstats.btic.hit * 100) / SD(mstats.btic.hit + mstats.btic.miss), mstats.btic.miss);
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} else
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} else
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printf("BTIC simulation disabled. Enabled it to see BTIC analysis\n");
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printf("BTIC simulation disabled. Enabled it to see BTIC analysis\n");
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|
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if (getsprbits(SPR_UPR, SPR_UPR_ICP)) {
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if (testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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printf("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss);
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printf("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss);
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} else
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} else
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printf("No ICache. Set UPR[ICP]\n");
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printf("No ICache. Set UPR[ICP]\n");
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|
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if (getsprbits(SPR_UPR, SPR_UPR_DCP)) {
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if (testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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printf("DC read: hit %d(%d%%), miss %d\n", dc_stats.readhit, (dc_stats.readhit * 100) / SD(dc_stats.readhit + dc_stats.readmiss), dc_stats.readmiss);
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printf("DC read: hit %d(%d%%), miss %d\n", dc_stats.readhit, (dc_stats.readhit * 100) / SD(dc_stats.readhit + dc_stats.readmiss), dc_stats.readmiss);
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printf("DC write: hit %d(%d%%), miss %d\n", dc_stats.writehit, (dc_stats.writehit * 100) / SD(dc_stats.writehit + dc_stats.writemiss), dc_stats.writemiss);
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printf("DC write: hit %d(%d%%), miss %d\n", dc_stats.writehit, (dc_stats.writehit * 100) / SD(dc_stats.writehit + dc_stats.writemiss), dc_stats.writemiss);
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} else
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} else
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printf("No DCache. Set UPR[DCP]\n");
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printf("No DCache. Set UPR[DCP]\n");
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|
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if (getsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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printf("IMMU read: hit %d(%d%%), miss %d\n", immu_stats.fetch_tlbhit, (immu_stats.fetch_tlbhit * 100) / SD(immu_stats.fetch_tlbhit + immu_stats.fetch_tlbmiss), immu_stats.fetch_tlbmiss);
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printf("IMMU read: hit %d(%d%%), miss %d\n", immu_stats.fetch_tlbhit, (immu_stats.fetch_tlbhit * 100) / SD(immu_stats.fetch_tlbhit + immu_stats.fetch_tlbmiss), immu_stats.fetch_tlbmiss);
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} else
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} else
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printf("No IMMU. Set UPR[IMP]\n");
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printf("No IMMU. Set UPR[IMP]\n");
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|
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if (getsprbits(SPR_UPR, SPR_UPR_DMP)) {
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if (testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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printf("DMMU read: hit %d(%d%%), miss %d\n", dmmu_stats.loads_tlbhit, (dmmu_stats.loads_tlbhit * 100) / SD(dmmu_stats.loads_tlbhit + dmmu_stats.loads_tlbmiss), dmmu_stats.loads_tlbmiss);
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printf("DMMU read: hit %d(%d%%), miss %d\n", dmmu_stats.loads_tlbhit, (dmmu_stats.loads_tlbhit * 100) / SD(dmmu_stats.loads_tlbhit + dmmu_stats.loads_tlbmiss), dmmu_stats.loads_tlbmiss);
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} else
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} else
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printf("No DMMU. Set UPR[DMP]\n");
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printf("No DMMU. Set UPR[DMP]\n");
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}
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}
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