Line 1... |
Line 1... |
/* execute.c -- OR1K architecture dependent simulation
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/* execute.c -- OR1K architecture dependent simulation
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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Line 100... |
Line 101... |
int do_stats = 0;
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int do_stats = 0;
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|
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/* Local data needed for execution. */
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/* Local data needed for execution. */
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static int next_delay_insn;
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static int next_delay_insn;
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static int breakpoint;
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static int breakpoint;
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static unsigned long *op;
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static int num_op;
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/* Effective address of instructions that have an effective address. This is
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* only used to get dump_exe_log correct */
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static unsigned long insn_ea;
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/* Implementation specific.
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/* Implementation specific.
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Get an actual value of a specific register. */
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Get an actual value of a specific register. */
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unsigned long evalsim_reg32(int regno)
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unsigned long evalsim_reg32(int regno)
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Line 180... |
Line 183... |
PRINTF("\nABORT: write out of registers\n");
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PRINTF("\nABORT: write out of registers\n");
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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}
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}
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}
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}
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/* Does srcoperand depend on computation of dstoperand? Return
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/* Implementation specific.
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Evaluates source operand opd. */
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static unsigned long eval_operand_val(unsigned long insn,
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struct insn_op_struct *opd)
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{
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unsigned long operand = 0;
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unsigned long sbit;
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unsigned int nbits = 0;
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while(1) {
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operand |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;
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nbits += opd->data;
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if(opd->type & OPTYPE_OP)
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break;
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opd++;
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}
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if(opd->type & OPTYPE_SIG) {
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sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
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if(operand & (1 << sbit)) operand |= 0xffffffff << sbit;
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}
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return operand;
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}
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/* Does source operand depend on computation of dstoperand? Return
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non-zero if yes.
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non-zero if yes.
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Cycle t Cycle t+1
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Cycle t Cycle t+1
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dst: irrelevant src: immediate always 0
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dst: irrelevant src: immediate always 0
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dst: reg1 direct src: reg2 direct 0 if reg1 != reg2
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dst: reg1 direct src: reg2 direct 0 if reg1 != reg2
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Line 199... |
Line 229... |
struct iqueue_entry *prev;
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struct iqueue_entry *prev;
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struct iqueue_entry *next;
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struct iqueue_entry *next;
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{
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{
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/* Find destination type. */
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/* Find destination type. */
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unsigned long type = 0;
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unsigned long type = 0;
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int i = 0;
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int prev_dis, next_dis;
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unsigned int prev_reg_val = 0;
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struct insn_op_struct *opd;
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if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG
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if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG
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&& or32_opcodes[next->insn_index].flags & OR32_R_FLAG)
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&& or32_opcodes[next->insn_index].flags & OR32_R_FLAG)
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return 1;
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return 1;
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while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST))
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opd = op_start[prev->insn_index];
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if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST)
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prev_dis = 0;
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{
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type = prev->op[i + MAX_OPERANDS];
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while (1) {
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if (opd->type & OPTYPE_DIS)
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prev_dis = 1;
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if (opd->type & OPTYPE_DST) {
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type = opd->type;
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if (prev_dis)
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type |= OPTYPE_DIS;
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/* Destination is always a register */
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prev_reg_val = eval_operand_val (prev->insn, opd);
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break;
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break;
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}
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}
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else
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if (opd->type & OPTYPE_LAST)
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i++;
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return 0; /* Doesn't have a destination operand */
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if (opd->type & OPTYPE_OP)
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prev_dis = 0;
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opd++;
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}
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/* We search all source operands - if we find confict => return 1 */
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/* We search all source operands - if we find confict => return 1 */
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i = 0;
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opd = op_start[next->insn_index];
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while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))
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next_dis = 0;
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if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))
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{
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while (1) {
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if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS) {
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if (opd->type & OPTYPE_DIS)
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if (type & OPTYPE_DIS)
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next_dis = 1;
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return 1;
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/* This instruction sequence also depends on order of execution:
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else if (next->op[i] == prev->op[i]
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* l.lw r1, k(r1)
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG))
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* l.sw k(r1), r4
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* Here r1 is a destination in l.sw */
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/* FIXME: This situation is not handeld here when r1 == r2:
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* l.sw k(r1), r4
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* l.lw r3, k(r2)
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*/
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if (!(opd->type & OPTYPE_DST) || (next_dis && (opd->type & OPTYPE_DST))) {
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if (opd->type & OPTYPE_REG)
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if (eval_operand_val (next->insn, opd) == prev_reg_val)
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return 1;
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return 1;
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}
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}
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if (next->op[i] == prev->op[i]
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if (opd->type & OPTYPE_LAST)
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG)
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break;
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&& (type & OPTYPE_REG))
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opd++;
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return 1;
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i++;
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}
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}
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else
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i++;
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return 0;
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return 0;
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}
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}
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/* Sets a new SPR_SR_OV value, based on next register value */
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/* Sets a new SPR_SR_OV value, based on next register value */
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Line 425... |
Line 476... |
}
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}
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/* Outputs dissasembled instruction */
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/* Outputs dissasembled instruction */
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void dump_exe_log ()
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void dump_exe_log ()
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{
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{
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unsigned long i = iqueue[0].insn_addr;
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unsigned long insn_addr = iqueue[0].insn_addr;
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unsigned long i, j;
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if (i == 0xffffffff) return;
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if (insn_addr == 0xffffffff) return;
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if (config.sim.exe_log_start <= runtime.cpu.instructions && (config.sim.exe_log_end <= 0 || runtime.cpu.instructions <= config.sim.exe_log_end)) {
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if ((config.sim.exe_log_start <= runtime.cpu.instructions) &&
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if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) {
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((config.sim.exe_log_end <= 0) ||
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(runtime.cpu.instructions <= config.sim.exe_log_end))) {
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if (config.sim.exe_log_marker &&
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!(runtime.cpu.instructions % config.sim.exe_log_marker)) {
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fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions);
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fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions);
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}
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}
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switch (config.sim.exe_log_type) {
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switch (config.sim.exe_log_type) {
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case EXE_LOG_HARDWARE:
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case EXE_LOG_HARDWARE:
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fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ", runtime.cpu.instructions, i);
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fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ",
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i), evalsim_mem8_void(i + 1));
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runtime.cpu.instructions, insn_addr);
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i + 2), evalsim_mem8_void(i + 3));
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(insn_addr),
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evalsim_mem8_void(insn_addr + 1));
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fprintf (runtime.sim.fexe_log, "%.2x%.2x",
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evalsim_mem8_void(insn_addr + 2),
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evalsim_mem8_void(insn_addr + 3));
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for(i = 0; i < MAX_GPRS; i++) {
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for(i = 0; i < MAX_GPRS; i++) {
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if (i % 4 == 0)
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if (i % 4 == 0)
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fprintf(runtime.sim.fexe_log, "\n");
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fprintf(runtime.sim.fexe_log, "\n");
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fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx ", i, reg[i]);
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fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx ", i, reg[i]);
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}
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}
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Line 455... |
Line 514... |
{
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{
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extern char *disassembled;
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extern char *disassembled;
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disassemble_index (iqueue[0].insn, iqueue[0].insn_index);
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disassemble_index (iqueue[0].insn, iqueue[0].insn_index);
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{
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{
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struct label_entry *entry;
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struct label_entry *entry;
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entry = get_label(i);
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entry = get_label(insn_addr);
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if (entry)
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if (entry)
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fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
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fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
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}
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}
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if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
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if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
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int i,j=0;
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struct insn_op_struct *opd = op_start[iqueue[0].insn_index];
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for (i = 0; i < num_op; i++)
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j = 0;
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if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
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while (1) {
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j=1;
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i = eval_operand_val (iqueue[0].insn, opd);
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fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", op[i],
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while (!(opd->type & OPTYPE_OP))
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peek_into_dtlb(op[i],0,0));
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opd++;
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} else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
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if (opd->type & OPTYPE_DIS) {
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fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", op[i],
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fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", insn_ea,
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evalsim_reg32 (op[i]));
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peek_into_dtlb(insn_ea,0,0));
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opd++; /* Skip of register operand */
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j++;
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} else if ((opd->type & OPTYPE_REG) && i) {
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fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", i,
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evalsim_reg32 (i));
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} else
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} else
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fprintf (runtime.sim.fexe_log, " ");
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fprintf (runtime.sim.fexe_log, " ");
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j++;
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i+=j;
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if(opd->type & OPTYPE_LAST)
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for (; i < 3; i++)
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break;
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opd++;
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}
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while(j < 3) {
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fprintf (runtime.sim.fexe_log, " ");
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fprintf (runtime.sim.fexe_log, " ");
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j++;
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}
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}
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fprintf (runtime.sim.fexe_log, "%.8lx ", i);
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}
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fprintf (runtime.sim.fexe_log, "%.8lx ", insn_addr);
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fprintf (runtime.sim.fexe_log, "%s\n", disassembled);
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fprintf (runtime.sim.fexe_log, "%s\n", disassembled);
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}
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}
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}
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}
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}
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}
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}
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}
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Line 628... |
Line 697... |
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|
|
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#define INSTRUCTION(name) void name (struct iqueue_entry *current)
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#define INSTRUCTION(name) void name (struct iqueue_entry *current)
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|
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/* Implementation specific.
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/* Implementation specific.
|
Parses and returns operands. */
|
Evaluates source operand op_no. */
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|
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static void
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static unsigned long eval_operand (int op_no, unsigned long insn_index,
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eval_operands (unsigned long insn, int insn_index, int* breakpoint)
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unsigned long insn)
|
{
|
{
|
struct insn_op_struct *opd = op_start[insn_index];
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struct insn_op_struct *opd = op_start[insn_index];
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unsigned long data = 0;
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unsigned long ret;
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int dis = 0;
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int no = 0;
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|
|
|
while (1)
|
while (op_no) {
|
{
|
if(opd->type & OPTYPE_LAST) {
|
unsigned long tmp = 0, nbits = 0;
|
fprintf (stderr, "Instruction requested more operands than it has\n");
|
while (1)
|
exit (1);
|
{
|
}
|
tmp |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;
|
if((opd->type & OPTYPE_OP) && !(opd->type & OPTYPE_DIS))
|
nbits += opd->data;
|
op_no--;
|
if (opd->type & OPTYPE_OP)
|
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break;
|
|
opd++;
|
opd++;
|
}
|
}
|
|
|
/* Do we have to sign extend? */
|
|
if (opd->type & OPTYPE_SIG)
|
|
{
|
|
int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
|
|
if (tmp & (1 << sbit))
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|
tmp |= 0xFFFFFFFF << sbit;
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|
}
|
|
if (opd->type & OPTYPE_DIS) {
|
if (opd->type & OPTYPE_DIS) {
|
/* We have to read register later. */
|
ret = eval_operand_val (insn, opd);
|
data += tmp;
|
while (!(opd->type & OPTYPE_OP))
|
dis = 1;
|
|
} else
|
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{
|
|
if (dis && (opd->type & OPTYPE_REG))
|
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op[no] = data + eval_reg32 (tmp);
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|
else
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|
op[no] = tmp;
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op[no + MAX_OPERANDS] = opd->type | (dis ? OPTYPE_DIS : 0);
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no++;
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data = 0;
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dis = 0;
|
|
}
|
|
if(opd->type & OPTYPE_LAST) {
|
|
num_op = no;
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return;
|
|
}
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opd++;
|
opd++;
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opd++;
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ret += eval_reg32 (eval_operand_val (insn, opd));
|
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insn_ea = ret;
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|
return ret;
|
}
|
}
|
num_op = no;
|
if (opd->type & OPTYPE_REG)
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return eval_reg32 (eval_operand_val (insn, opd));
|
|
|
|
return eval_operand_val (insn, opd);
|
}
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}
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|
|
/* Implementation specific.
|
/* Implementation specific.
|
Evaluates source operand op_no. */
|
Set destination operand (reister direct) with value. */
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|
|
static unsigned long eval_operand (int op_no)
|
inline static void set_operand(int op_no, unsigned long value,
|
|
unsigned long insn_index, unsigned long insn)
|
{
|
{
|
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
|
struct insn_op_struct *opd = op_start[insn_index];
|
return op[op_no];
|
|
} else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {
|
while (op_no) {
|
return eval_reg32 (op[op_no]);
|
if(opd->type & OPTYPE_LAST) {
|
} else {
|
fprintf (stderr, "Instruction requested more operands than it has\n");
|
return op[op_no];
|
exit (1);
|
}
|
}
|
|
if((opd->type & OPTYPE_OP) && !(opd->type & OPTYPE_DIS))
|
|
op_no--;
|
|
opd++;
|
}
|
}
|
|
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/* Implementation specific.
|
if (!(opd->type & OPTYPE_REG)) {
|
Set destination operand (reister direct) with value. */
|
|
|
|
inline static void set_operand(int op_no, unsigned long value)
|
|
{
|
|
/* Mark this as destination operand. */
|
|
if (!(op[op_no + MAX_OPERANDS] & OPTYPE_REG)) {
|
|
fprintf (stderr, "Trying to set a non-register operand\n");
|
fprintf (stderr, "Trying to set a non-register operand\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
set_reg32(op[op_no], value);
|
set_reg32 (eval_operand_val (insn, opd), value);
|
}
|
}
|
|
|
/* Simple and rather slow decoding function based on built automata. */
|
/* Simple and rather slow decoding function based on built automata. */
|
static inline void decode_execute (struct iqueue_entry *current)
|
static inline void decode_execute (struct iqueue_entry *current)
|
{
|
{
|
Line 718... |
Line 765... |
current->insn_index = insn_index = insn_decode(current->insn);
|
current->insn_index = insn_index = insn_decode(current->insn);
|
|
|
if (insn_index < 0)
|
if (insn_index < 0)
|
l_invalid(current);
|
l_invalid(current);
|
else {
|
else {
|
op = ¤t->op[0];
|
|
eval_operands (current->insn, insn_index, &breakpoint);
|
|
or32_opcodes[insn_index].exec(current);
|
or32_opcodes[insn_index].exec(current);
|
}
|
}
|
if (do_stats) analysis(&iqueue[0]);
|
if (do_stats) analysis(&iqueue[0]);
|
}
|
}
|
|
|
#define SET_PARAM0(val) set_operand(0, val)
|
#define SET_PARAM0(val) set_operand(0, val, current->insn_index, current->insn)
|
|
|
#define PARAM0 eval_operand(0)
|
#define PARAM0 eval_operand(0, current->insn_index, current->insn)
|
#define PARAM1 eval_operand(1)
|
#define PARAM1 eval_operand(1, current->insn_index, current->insn)
|
#define PARAM2 eval_operand(2)
|
#define PARAM2 eval_operand(2, current->insn_index, current->insn)
|
|
|
#include "insnset.c"
|
#include "insnset.c"
|
|
|
#endif /* !SIMPLE_EXECUTION */
|
#endif /* !SIMPLE_EXECUTION */
|
|
|
No newline at end of file
|
No newline at end of file
|