| Line 17... |
Line 17... |
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
*/
|
*/
|
|
|
/* get a prototype for 'register_memoryarea() */
|
/* get a prototype for 'register_memoryarea()', and 'adjust_rw_delay()' */
|
#include "abstract.h"
|
#include "abstract.h"
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#include "sim-config.h"
|
#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
|
|
|
#include "atahost.h"
|
/* all user defineable settings are in 'atahost_define.h' */
|
#include "atahost_define.h"
|
#include "atahost_define.h"
|
|
#include "atahost.h"
|
#include "messages.h"
|
#include "messages.h"
|
|
|
static ata_host atas[MAX_ATAS];
|
static ata_host atas[MAX_ATAS];
|
|
|
/* reset and initialize ATA host core(s) */
|
/* reset and initialize ATA host core(s) */
|
| Line 43... |
Line 44... |
{
|
{
|
ata = &(atas[i]);
|
ata = &(atas[i]);
|
|
|
// reset the core registers
|
// reset the core registers
|
ata->regs.ctrl = 0x0001;
|
ata->regs.ctrl = 0x0001;
|
ata->regs.stat = (DEV_ID << 24) | (REV << 20);
|
ata->regs.stat = (DEV_ID << 28) | (REV << 24);
|
ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
| Line 63... |
Line 64... |
ata->devices.device0.packet = config.atas[i].dev_packet0;
|
ata->devices.device0.packet = config.atas[i].dev_packet0;
|
ata->devices.device1.size = config.atas[i].dev_size1;
|
ata->devices.device1.size = config.atas[i].dev_size1;
|
ata->devices.device1.type = config.atas[i].dev_type1;
|
ata->devices.device1.type = config.atas[i].dev_type1;
|
ata->devices.device1.packet = config.atas[i].dev_packet1;
|
ata->devices.device1.packet = config.atas[i].dev_packet1;
|
|
|
|
// inform simulator about new read/write delay timings
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
|
|
/* initialize simulator & ata_devices */
|
/* initialize simulator & ata_devices */
|
if (!first_time)
|
if (!first_time)
|
{
|
{
|
/* Connect ata_devices. */
|
/* Connect ata_devices. */
|
ata_devices_init(&ata->devices, config.atas[i].dev_file0, config.atas[i].dev_file1);
|
ata_devices_init(&ata->devices, config.atas[i].dev_file0, config.atas[i].dev_file1);
|
| Line 121... |
Line 125... |
return 0;
|
return 0;
|
}
|
}
|
|
|
/* determine if ata_host or ata_device addressed */
|
/* determine if ata_host or ata_device addressed */
|
if (is_ata_hostadr(addr))
|
if (is_ata_hostadr(addr))
|
|
{
|
|
// Accesses to internal register take 2cycles
|
|
adjust_rw_delay( ata->baseaddr, 2, 2 );
|
|
|
switch( addr ) {
|
switch( addr ) {
|
case ATA_CTRL :
|
case ATA_CTRL :
|
return ata -> regs.ctrl;
|
return ata -> regs.ctrl;
|
|
|
case ATA_STAT :
|
case ATA_STAT :
|
| Line 153... |
Line 161... |
#endif
|
#endif
|
|
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
|
}
|
|
else
|
|
{
|
|
// make sure simulator uses correct read/write delay timings
|
|
#if (DEV_ID > 1)
|
|
if ( (addr & 0x7f) == ATA_DR)
|
|
{
|
|
if (ata->devices.dev)
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
|
|
else
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
|
|
}
|
else
|
else
|
|
#endif
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
|
|
return ata_devices_read(&ata->devices, addr & 0x7f);
|
return ata_devices_read(&ata->devices, addr & 0x7f);
|
}
|
}
|
|
}
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/*
|
/*
|
Write a register
|
Write a register
|
| Line 174... |
Line 198... |
return;
|
return;
|
}
|
}
|
|
|
/* determine if ata_host or ata_device addressed */
|
/* determine if ata_host or ata_device addressed */
|
if (is_ata_hostadr(addr))
|
if (is_ata_hostadr(addr))
|
|
{
|
|
// Accesses to internal register take 2cycles
|
|
adjust_rw_delay( ata->baseaddr, 2, 2 );
|
|
|
switch( addr ) {
|
switch( addr ) {
|
case ATA_CTRL :
|
case ATA_CTRL :
|
ata -> regs.ctrl = value;
|
ata -> regs.ctrl = value;
|
|
|
/* check if reset bit set, if so reset ata-devices */
|
/* check if reset bit set, if so reset ata-devices */
|
| Line 224... |
Line 252... |
But when using 'DM'-simulator-command, the screen gets filled with these messages.
|
But when using 'DM'-simulator-command, the screen gets filled with these messages.
|
Thereby eradicating the usefulness of the message
|
Thereby eradicating the usefulness of the message
|
*/
|
*/
|
break;
|
break;
|
}
|
}
|
|
}
|
else
|
else
|
|
{
|
|
// make sure simulator uses correct read/write delay timings
|
|
#if (DEV_ID > 1)
|
|
if ( (addr & 0x7f) == ATA_DR)
|
|
{
|
|
if (ata->devices.dev)
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
|
|
else
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
|
|
}
|
|
else
|
|
#endif
|
|
adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
|
|
ata_devices_write(&ata->devices, addr & 0x7f, value);
|
ata_devices_write(&ata->devices, addr & 0x7f, value);
|
}
|
}
|
|
}
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/* Dump status */
|
/* Dump status */
|
void ata_status( void )
|
void ata_status( void )
|
