| Line 30... |
Line 30... |
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#include "mc.h"
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#include "mc.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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extern struct dev_memarea *dev_list;
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static struct mc mc;
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static struct mc mc;
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void set_csc_tms (int i, unsigned long csc, unsigned long tms) {
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void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {
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if (1);
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struct dev_memarea *mem_dev = dev_list;
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while (mem_dev) {
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if (mem_dev->chip_select == cs) {
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printf("CS0 addr_mask = %.8lx addr_compare = %.8lx\n", mem_dev->addr_mask, mem_dev->addr_compare);
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mem_dev->addr_mask = mc.ba_mask << 21;
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mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) & 0xff) << 21;
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
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mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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mem_dev->delayr = 2;
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mem_dev->delayw = 2;
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mem_dev->delayr = 2;
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mem_dev->delayw = 2;
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}
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break;
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}
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mem_dev = mem_dev->next;
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}
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}
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}
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/* Set a specific MC register with value. */
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/* Set a specific MC register with value. */
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void mc_write_word(unsigned long addr, unsigned long value)
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void mc_write_word(unsigned long addr, unsigned long value)
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{
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{
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| Line 53... |
Line 79... |
break;
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break;
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case MC_POC:
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case MC_POC:
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fprintf (stderr, "warning: write to MC's POC register!");
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fprintf (stderr, "warning: write to MC's POC register!");
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break;
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break;
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case MC_BA_MASK:
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case MC_BA_MASK:
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mc.ba_mask = value;
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mc.ba_mask = value & MC_BA_MASK_VALID;
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break;
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break;
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default:
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default:
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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addr -= MC_CSC(0);
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addr -= MC_CSC(0);
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if ((addr >> 2) & 1)
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if ((addr >> 2) & 1)
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| Line 112... |
Line 138... |
if (config.mc.enabled) {
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if (config.mc.enabled) {
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printf("Resetting memory controller.\n");
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printf("Resetting memory controller.\n");
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memset(&mc, 0, sizeof(struct mc));
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memset(&mc, 0, sizeof(struct mc));
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mc.poc = config.mc.POC;
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mc.poc = config.mc.POC;
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/* Set CS0 */
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mc.csc[0] = (((config.mc.POC & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((config.mc.POC & 0x03) << MC_CSC_BW_OFFSET) | 1;
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if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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mc.tms[0] = MC_TMS_ASYNC_VALID;
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} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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mc.tms[0] = MC_TMS_SDRAM_VALID;
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} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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mc.tms[0] = MC_TMS_SSRAM_VALID;
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} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mc.tms[0] = MC_TMS_SYNC_VALID;
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}
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set_csc_tms (0, mc.csc[0], mc.tms[0]);
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register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);
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register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);
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}
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}
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}
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}
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inline void mc_clock()
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inline void mc_clock()
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