URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [nog_patch_50/] [or1ksim/] [cpu/] [or1k/] [spr_defs.h] - Diff between revs 102 and 133

Rev 102	Rev 133
Line 108...	Line 108...
`#define SPR_PICMR (SPRGROUP_PIC + 0)`	`#define SPR_PICMR (SPRGROUP_PIC + 0)`
`#define SPR_PICPR (SPRGROUP_PIC + 1)`	`#define SPR_PICPR (SPRGROUP_PIC + 1)`
`#define SPR_PICSR (SPRGROUP_PIC + 2)`	`#define SPR_PICSR (SPRGROUP_PIC + 2)`

`/* Tick Timer group */`	`/* Tick Timer group */`
`#define SPR_TTCR (SPRGROUP_TT + 0)`	`#define SPR_TTMR (SPRGROUP_TT + 0)`
`#define SPR_TTIR (SPRGROUP_TT + 1)`	`#define SPR_TTCR (SPRGROUP_TT + 1)`

`/*`	`/*`
`* Bit definitions for the Version Register`	`* Bit definitions for the Version Register`
`*`	`*`
`*/`	`*/`
Line 380...	Line 380...
`/*`	`/*`
`* Bit definitions for Tick Timer Control Register`	`* Bit definitions for Tick Timer Control Register`
`*`	`*`
`*/`	`*/`
`#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */`	`#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */`
`#define SPR_TTCR_IP 0x10000000 /* Interrupt Present */`	`#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD`
`#define SPR_TTCR_IE 0x20000000 /* Interrupt Enable */`	`#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */`
`#define SPR_TTCR_SR 0x40000000 /* Single Run */`	`#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */`
`#define SPR_TTCR_TTE 0x80000000 /* Tick Timer Enable */`	`#define SPR_TTMR_M 0xC0000000 /* Tick Timer Mode */`


`No newline at end of file`	`No newline at end of file`