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#define SPRGROUP_DMMU 0x01000000
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#define SPRGROUP_DMMU 0x01000000
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#define SPRGROUP_IMMU 0x02000000
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#define SPRGROUP_IMMU 0x02000000
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#define SPRGROUP_DC 0x03000000
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#define SPRGROUP_DC 0x03000000
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#define SPRGROUP_IC 0x04000000
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#define SPRGROUP_IC 0x04000000
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#define SPRGROUP_MAC 0x05000000
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#define SPRGROUP_MAC 0x05000000
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#define SPRGROUP_TT 0x09000000
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_MPR (SPRGROUP_SYS + 1)
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#define SPR_MPR (SPRGROUP_SYS + 1)
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#define SPR_SR (SPRGROUP_SYS + 2)
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#define SPR_SR (SPRGROUP_SYS + 2)
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/* MAC group */
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/* MAC group */
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#define SPR_MACLO (SPRGROUP_MAC + 1)
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#define SPR_MACLO (SPRGROUP_MAC + 1)
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#define SPR_MACHI (SPRGROUP_MAC + 2)
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#define SPR_MACHI (SPRGROUP_MAC + 2)
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/* Tick Timer group */
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#define SPR_TTCR (SPRGROUP_TT + 0)
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/*
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/*
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* Bit definitions for the Version Register
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* Bit definitions for the Version Register
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*
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*
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*/
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*/
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_ITLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */
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#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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/*
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* Bit definitions for Tick Timer Control Register
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*
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*/
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTCR_IP 0x10000000 /* Interrupt Present */
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#define SPR_TTCR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTCR_SR 0x40000000 /* Single Run */
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#define SPR_TTCR_TTE 0x80000000 /* Tick Timer Enable */
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