| Line 156... |
Line 156... |
/*
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/*
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* Bit definitions for the Supervision Register
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* Bit definitions for the Supervision Register
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*
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*
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*/
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_PXR 0x00008000 /* Partial exception recognition */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_EP 0x00004000 /* Exception Prefix */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
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/*
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/*
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* Bit definitions for the Data MMU Control Register
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* Bit definitions for the Data MMU Control Register
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*
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*
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*/
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*/
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*/
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*/
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#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DSR_LPINTE 0x00000010 /* Low priority interrupt exception */
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#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */
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#define SPR_DSR_AE 0x00000020 /* Alignment exception */
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#define SPR_DSR_AE 0x00000020 /* Alignment exception */
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#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DSR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
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#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
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*/
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*/
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#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DRR_LPINTE 0x00000010 /* Low priority interrupt exception */
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#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
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#define SPR_DRR_AE 0x00000020 /* Alignment exception */
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#define SPR_DRR_AE 0x00000020 /* Alignment exception */
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#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DRR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_TE 0x00001000 /* Trap exception */
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#define SPR_DRR_TE 0x00001000 /* Trap exception */
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