| Line 37... |
Line 37... |
#include "dma.h"
|
#include "dma.h"
|
#include "sim-config.h"
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#include "sim-config.h"
|
#include "pic.h"
|
#include "pic.h"
|
#include "abstract.h"
|
#include "abstract.h"
|
#include "fields.h"
|
#include "fields.h"
|
|
#include "sched.h"
|
#include "debug.h"
|
#include "debug.h"
|
|
|
/* The representation of the DMA controllers */
|
/* We keep a copy of all our controllers because we have to export an interface
|
static struct dma_controller dmas[MAX_DMAS];
|
* to other peripherals eg. ethernet */
|
|
static struct dma_controller *dmas = NULL;
|
|
|
static uint32_t dma_read32( oraddr_t addr, void *dat );
|
static uint32_t dma_read32( oraddr_t addr, void *dat );
|
static void dma_write32( oraddr_t addr, uint32_t value, void *dat );
|
static void dma_write32( oraddr_t addr, uint32_t value, void *dat );
|
|
|
static unsigned long dma_read_ch_csr( struct dma_channel *channel );
|
static unsigned long dma_read_ch_csr( struct dma_channel *channel );
|
static void dma_write_ch_csr( struct dma_channel *channel, unsigned long value );
|
static void dma_write_ch_csr( struct dma_channel *channel, unsigned long value );
|
static void dma_controller_clock( struct dma_controller *dma );
|
void dma_controller_clock( struct dma_controller *dma );
|
static void dma_load_descriptor( struct dma_channel *channel );
|
static void dma_load_descriptor( struct dma_channel *channel );
|
static void dma_init_transfer( struct dma_channel *channel );
|
static void dma_init_transfer( struct dma_channel *channel );
|
static void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt );
|
static void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt );
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|
|
static void masked_increase( unsigned long *value, unsigned long mask );
|
void dma_channel_clock( void *dat );
|
|
|
|
static void masked_increase( oraddr_t *value, unsigned long mask );
|
|
|
#define CHANNEL_ND_I(ch) (TEST_FLAG(ch->regs.csr,DMA_CH_CSR,MODE) && TEST_FLAG(ch->regs.csr,DMA_CH_CSR,USE_ED) && ch->dma_nd_i)
|
#define CHANNEL_ND_I(ch) (TEST_FLAG(ch->regs.csr,DMA_CH_CSR,MODE) && TEST_FLAG(ch->regs.csr,DMA_CH_CSR,USE_ED) && ch->dma_nd_i)
|
|
|
|
|
/* Reset. Initializes all registers to default and places devices in memory address space. */
|
/* Reset. Initializes all registers to default and places devices in memory address space. */
|
void dma_reset()
|
void dma_reset(void *dat)
|
{
|
{
|
unsigned i;
|
struct dma_controller *dma = dat;
|
|
unsigned channel_number;
|
|
|
memset( dmas, 0, sizeof(dmas) );
|
memset( dma->ch, 0, sizeof(dma->ch) );
|
|
|
for ( i = 0; i < config.ndmas; ++ i ) {
|
dma->regs.csr = 0;
|
struct dma_controller *dma = &(dmas[i]);
|
dma->regs.int_msk_a = 0;
|
unsigned channel_number;
|
dma->regs.int_msk_b = 0;
|
|
dma->regs.int_src_a = 0;
|
|
dma->regs.int_src_b = 0;
|
|
|
dma->baseaddr = config.dmas[i].baseaddr;
|
|
dma->irq = config.dmas[i].irq;
|
|
for ( channel_number = 0; channel_number < DMA_NUM_CHANNELS; ++ channel_number ) {
|
for ( channel_number = 0; channel_number < DMA_NUM_CHANNELS; ++ channel_number ) {
|
dma->ch[channel_number].controller = &(dmas[i]);
|
dma->ch[channel_number].controller = dma;
|
dma->ch[channel_number].channel_number = channel_number;
|
dma->ch[channel_number].channel_number = channel_number;
|
dma->ch[channel_number].channel_mask = 1LU << channel_number;
|
dma->ch[channel_number].channel_mask = 1LU << channel_number;
|
dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
|
dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
|
}
|
}
|
if ( dma->baseaddr != 0 )
|
|
register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, 0, dma_read32, dma_write32, NULL );
|
|
}
|
|
}
|
}
|
|
|
/* Print register values on stdout */
|
/* Print register values on stdout */
|
void dma_status( void )
|
void dma_status( void *dat )
|
{
|
{
|
unsigned i, j;
|
unsigned i, j;
|
|
struct dma_controller *dma = dat;
|
for ( i = 0; i < config.ndmas; ++ i ) {
|
|
struct dma_controller *dma = &(dmas[i]);
|
|
|
|
if ( dma->baseaddr == 0 )
|
if ( dma->baseaddr == 0 )
|
continue;
|
return;
|
|
|
PRINTF( "\nDMA controller %u at 0x%"PRIxADDR":\n", i, dma->baseaddr );
|
PRINTF( "\nDMA controller %u at 0x%"PRIxADDR":\n", i, dma->baseaddr );
|
PRINTF( "CSR : 0x%08lX\n", dma->regs.csr );
|
PRINTF( "CSR : 0x%08lX\n", dma->regs.csr );
|
PRINTF( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
|
PRINTF( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
|
PRINTF( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
|
PRINTF( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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| Line 113... |
Line 113... |
PRINTF( "CH%u_AM1 : 0x%08lX\n", j, channel->regs.am1 );
|
PRINTF( "CH%u_AM1 : 0x%08lX\n", j, channel->regs.am1 );
|
PRINTF( "CH%u_DESC : 0x%08lX\n", j, channel->regs.desc );
|
PRINTF( "CH%u_DESC : 0x%08lX\n", j, channel->regs.desc );
|
PRINTF( "CH%u_SWPTR : 0x%08lX\n", j, channel->regs.swptr );
|
PRINTF( "CH%u_SWPTR : 0x%08lX\n", j, channel->regs.swptr );
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
|
/* Read a register */
|
/* Read a register */
|
uint32_t dma_read32( oraddr_t addr, void *dat )
|
uint32_t dma_read32( oraddr_t addr, void *dat )
|
{
|
{
|
unsigned i;
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = NULL;
|
|
|
|
for ( i = 0; i < MAX_DMAS && dma == NULL; ++ i ) {
|
|
if ( addr >= dmas[i].baseaddr && addr < dmas[i].baseaddr + DMA_ADDR_SPACE )
|
|
dma = &(dmas[i]);
|
|
}
|
|
|
|
/* verify we found a controller */
|
|
if ( dma == NULL ) {
|
|
fprintf( stderr, "dma_read32( 0x%"PRIxADDR" ): Out of range\n", addr );
|
|
runtime.sim.cont_run = 0;
|
|
return 0;
|
|
}
|
|
|
|
addr -= dma->baseaddr;
|
addr -= dma->baseaddr;
|
|
|
if ( addr % 4 != 0 ) {
|
if ( addr % 4 != 0 ) {
|
fprintf( stderr, "dma_read32( 0x%"PRIxADDR" ): Not register-aligned\n",
|
fprintf( stderr, "dma_read32( 0x%"PRIxADDR" ): Not register-aligned\n",
|
| Line 172... |
Line 158... |
case DMA_CH_AM1: return dma->ch[chno].regs.am1;
|
case DMA_CH_AM1: return dma->ch[chno].regs.am1;
|
case DMA_CH_DESC: return dma->ch[chno].regs.desc;
|
case DMA_CH_DESC: return dma->ch[chno].regs.desc;
|
case DMA_CH_SWPTR: return dma->ch[chno].regs.swptr;
|
case DMA_CH_SWPTR: return dma->ch[chno].regs.swptr;
|
}
|
}
|
}
|
}
|
|
return 0;
|
}
|
}
|
|
|
|
|
/* Handle read from a channel CSR */
|
/* Handle read from a channel CSR */
|
unsigned long dma_read_ch_csr( struct dma_channel *channel )
|
unsigned long dma_read_ch_csr( struct dma_channel *channel )
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| Line 194... |
Line 181... |
|
|
|
|
/* Write a register */
|
/* Write a register */
|
void dma_write32( oraddr_t addr, uint32_t value, void *dat )
|
void dma_write32( oraddr_t addr, uint32_t value, void *dat )
|
{
|
{
|
unsigned i;
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = NULL;
|
|
|
|
/* Find which controller this is */
|
|
for ( i = 0; i < MAX_DMAS && dma == NULL; ++ i ) {
|
|
if ( (addr >= dmas[i].baseaddr) && (addr < dmas[i].baseaddr + DMA_ADDR_SPACE) )
|
|
dma = &(dmas[i]);
|
|
}
|
|
|
|
/* verify we found a controller */
|
|
if ( dma == NULL ) {
|
|
fprintf( stderr, "dma_write32( 0x%"PRIxADDR" ): Out of range\n", addr );
|
|
runtime.sim.cont_run = 0;
|
|
return;
|
|
}
|
|
|
|
addr -= dma->baseaddr;
|
addr -= dma->baseaddr;
|
|
|
if ( addr % 4 != 0 ) {
|
if ( addr % 4 != 0 ) {
|
fprintf( stderr, "dma_write32( 0x%"PRIxADDR", 0x%08"PRIx32" ): Not register-aligned\n", addr + dma->baseaddr, value );
|
fprintf( stderr, "dma_write32( 0x%"PRIxADDR", 0x%08"PRIx32" ): Not register-aligned\n", addr + dma->baseaddr, value );
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| Line 261... |
Line 234... |
/* Write a channel CSR
|
/* Write a channel CSR
|
* This ensures only the writable bits are modified.
|
* This ensures only the writable bits are modified.
|
*/
|
*/
|
void dma_write_ch_csr( struct dma_channel *channel, unsigned long value )
|
void dma_write_ch_csr( struct dma_channel *channel, unsigned long value )
|
{
|
{
|
|
/* Check if we should *start* a transfer */
|
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) &&
|
|
TEST_FLAG( value, DMA_CH_CSR, CH_EN ))
|
|
SCHED_ADD( dma_channel_clock, channel, runtime.sim.cycles + 1 );
|
|
else if ( !TEST_FLAG( value, DMA_CH_CSR, CH_EN ) )
|
|
/* The CH_EN flag is clear, check if we have a transfer in progress and
|
|
* clear it */
|
|
SCHED_FIND_REMOVE( dma_channel_clock, channel );
|
|
|
/* Copy the writable bits to the channel CSR */
|
/* Copy the writable bits to the channel CSR */
|
channel->regs.csr &= ~DMA_CH_CSR_WRITE_MASK;
|
channel->regs.csr &= ~DMA_CH_CSR_WRITE_MASK;
|
channel->regs.csr |= value & DMA_CH_CSR_WRITE_MASK;
|
channel->regs.csr |= value & DMA_CH_CSR_WRITE_MASK;
|
}
|
}
|
|
|
|
|
/*
|
|
* Simulation of control signals
|
|
* To be used by simulations for other devices, e.g. ethernet
|
|
*/
|
|
|
|
void set_dma_req_i( unsigned dma_controller, unsigned channel )
|
/* Clock tick for one channel on one DMA controller.
|
{
|
|
dmas[dma_controller].ch[channel].dma_req_i = 1;
|
|
}
|
|
|
|
void clear_dma_req_i( unsigned dma_controller, unsigned channel )
|
|
{
|
|
dmas[dma_controller].ch[channel].dma_req_i = 0;
|
|
}
|
|
|
|
void set_dma_nd_i( unsigned dma_controller, unsigned channel )
|
|
{
|
|
dmas[dma_controller].ch[channel].dma_nd_i = 1;
|
|
}
|
|
|
|
void clear_dma_nd_i( unsigned dma_controller, unsigned channel )
|
|
{
|
|
dmas[dma_controller].ch[channel].dma_nd_i = 0;
|
|
}
|
|
|
|
unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel )
|
|
{
|
|
return dmas[dma_controller].ch[channel].dma_ack_o;
|
|
}
|
|
|
|
|
|
|
|
/* Simulation hook. Must be called every clock cycle to simulate DMA. */
|
|
void dma_clock()
|
|
{
|
|
unsigned i;
|
|
for ( i = 0; i < MAX_DMAS; ++ i ) {
|
|
if ( dmas[i].baseaddr != 0 )
|
|
dma_controller_clock( &(dmas[i]) );
|
|
}
|
|
}
|
|
|
|
|
|
/* Clock tick for one DMA controller.
|
|
* This does the actual "DMA" operation.
|
* This does the actual "DMA" operation.
|
* One chunk is transferred per clock.
|
* One chunk is transferred per clock.
|
*/
|
*/
|
void dma_controller_clock( struct dma_controller *dma )
|
void dma_channel_clock( void *dat )
|
{
|
{
|
unsigned chno;
|
|
int breakpoint = 0;
|
int breakpoint = 0;
|
|
struct dma_channel *channel = dat;
|
for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno ) {
|
|
struct dma_channel *channel = &(dma->ch[chno]);
|
|
|
|
/* check if this channel is enabled */
|
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
|
|
continue;
|
|
|
|
/* Do we need to abort? */
|
/* Do we need to abort? */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
|
debug( 3, "DMA: STOP requested\n" );
|
debug( 3, "DMA: STOP requested\n" );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
|
| Line 340... |
Line 273... |
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
report_interrupt( channel->controller->irq );
|
report_interrupt( channel->controller->irq );
|
}
|
}
|
|
|
continue;
|
return;
|
}
|
}
|
|
|
/* In HW Handshake mode, only work when dma_req_i asserted */
|
/* In HW Handshake mode, only work when dma_req_i asserted */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, MODE ) &&
|
if ( TEST_FLAG(channel->regs.csr, DMA_CH_CSR, MODE) && !channel->dma_req_i ) {
|
!channel->dma_req_i ) {
|
/* Reschedule */
|
continue;
|
SCHED_ADD( dma_channel_clock, dat, runtime.sim.cycles + 1 );
|
|
return;
|
}
|
}
|
|
|
/* If this is the first cycle of the transfer, initialize our state */
|
/* If this is the first cycle of the transfer, initialize our state */
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
|
debug( 4, "DMA: Starting new transfer\n" );
|
debug( 4, "DMA: Starting new transfer\n" );
|
| Line 370... |
Line 304... |
|
|
/* Might need to skip descriptor */
|
/* Might need to skip descriptor */
|
if ( CHANNEL_ND_I( channel ) ) {
|
if ( CHANNEL_ND_I( channel ) ) {
|
debug( 3, "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
|
debug( 3, "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
|
dma_channel_terminate_transfer( channel, 0 );
|
dma_channel_terminate_transfer( channel, 0 );
|
continue;
|
return;
|
}
|
}
|
}
|
}
|
|
|
/* Transfer one word */
|
/* Transfer one word */
|
set_mem32( channel->destination, eval_mem32( channel->source, &breakpoint ), &breakpoint );
|
set_mem32( channel->destination, eval_mem32( channel->source, &breakpoint ), &breakpoint );
|
| Line 389... |
Line 323... |
|
|
/* When done with a chunk, check for dma_nd_i */
|
/* When done with a chunk, check for dma_nd_i */
|
if ( CHANNEL_ND_I( channel ) ) {
|
if ( CHANNEL_ND_I( channel ) ) {
|
debug( 3, "DMA: dma_nd_i asserted\n" );
|
debug( 3, "DMA: dma_nd_i asserted\n" );
|
dma_channel_terminate_transfer( channel, 0 );
|
dma_channel_terminate_transfer( channel, 0 );
|
continue;
|
return;
|
}
|
}
|
|
|
/* Are we done? */
|
/* Are we done? */
|
if ( channel->words_transferred >= channel->total_size )
|
if ( channel->words_transferred >= channel->total_size ) {
|
dma_channel_terminate_transfer( channel, 1 );
|
dma_channel_terminate_transfer( channel, 1 );
|
|
return;
|
}
|
}
|
|
|
|
/* Reschedule to transfer the next chunk */
|
|
SCHED_ADD( dma_channel_clock, dat, runtime.sim.cycles + 1 );
|
}
|
}
|
|
|
|
|
/* Copy relevant valued from linked list descriptor to channel registers */
|
/* Copy relevant valued from linked list descriptor to channel registers */
|
void dma_load_descriptor( struct dma_channel *channel )
|
void dma_load_descriptor( struct dma_channel *channel )
|
| Line 446... |
Line 384... |
|
|
/* Might be working in a linked list */
|
/* Might be working in a linked list */
|
if ( channel->load_next_descriptor_when_done ) {
|
if ( channel->load_next_descriptor_when_done ) {
|
dma_load_descriptor( channel );
|
dma_load_descriptor( channel );
|
dma_init_transfer( channel );
|
dma_init_transfer( channel );
|
|
/* Reschedule */
|
|
SCHED_ADD( dma_channel_clock, channel, runtime.sim.cycles + 1 );
|
return;
|
return;
|
}
|
}
|
|
|
/* Might be in auto-restart mode */
|
/* Might be in auto-restart mode */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
|
| Line 482... |
Line 422... |
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Utility function: Add 4 to a value with a mask */
|
/* Utility function: Add 4 to a value with a mask */
|
void masked_increase( unsigned long *value, unsigned long mask )
|
static void masked_increase( oraddr_t *value, unsigned long mask )
|
{
|
{
|
*value = (*value & ~mask) | ((*value + 4) & mask);
|
*value = (*value & ~mask) | ((*value + 4) & mask);
|
}
|
}
|
|
|
/*----------------------------------------------------[ DMA configuration ]---*/
|
/*-------------------------------------------[ DMA<->Peripheral interface ]---*/
|
void dma_ndmas(union param_val val, void *dat)
|
/*
|
|
* Simulation of control signals
|
|
* To be used by simulations for other devices, e.g. ethernet
|
|
*/
|
|
|
|
void set_dma_req_i( struct dma_channel *channel )
|
{
|
{
|
if (val.int_val >= 0 && val.int_val < MAX_DMAS)
|
channel->dma_req_i = 1;
|
config.ndmas = val.int_val;
|
}
|
else
|
|
CONFIG_ERROR("invalid number of devices.");
|
void clear_dma_req_i( struct dma_channel *channel )
|
|
{
|
|
channel->dma_req_i = 0;
|
|
}
|
|
|
|
void set_dma_nd_i( struct dma_channel *channel )
|
|
{
|
|
channel->dma_nd_i = 1;
|
|
}
|
|
|
|
void clear_dma_nd_i( struct dma_channel *channel )
|
|
{
|
|
channel->dma_nd_i = 0;
|
|
}
|
|
|
|
unsigned check_dma_ack_o( struct dma_channel *channel )
|
|
{
|
|
return channel->dma_ack_o;
|
}
|
}
|
|
|
|
struct dma_channel *find_dma_controller_ch( unsigned controller,
|
|
unsigned channel )
|
|
{
|
|
struct dma_controller *cur = dmas;
|
|
|
|
while( cur && controller ) {
|
|
cur = cur->next;
|
|
controller--;
|
|
}
|
|
|
|
if( !cur )
|
|
return NULL;
|
|
|
|
return &(cur->ch[channel]);
|
|
}
|
|
|
|
|
|
/*----------------------------------------------------[ DMA configuration ]---*/
|
void dma_baseaddr(union param_val val, void *dat)
|
void dma_baseaddr(union param_val val, void *dat)
|
{
|
{
|
if (current_device >= 0 && current_device < config.ndmas)
|
struct dma_controller *dma = dat;
|
config.dmas[current_device].baseaddr = val.addr_val;
|
dma->baseaddr = val.addr_val;
|
else
|
|
CONFIG_ERROR("invalid device number.");
|
|
}
|
}
|
|
|
void dma_irq(union param_val val, void *dat)
|
void dma_irq(union param_val val, void *dat)
|
{
|
{
|
if (current_device >= 0 && current_device < config.ndmas)
|
struct dma_controller *dma = dat;
|
config.dmas[current_device].irq = val.int_val;
|
dma->irq = val.int_val;
|
else
|
|
CONFIG_ERROR("invalid device number.");
|
|
}
|
}
|
|
|
void dma_vapi_id(union param_val val, void *dat)
|
void dma_vapi_id(union param_val val, void *dat)
|
{
|
{
|
if (current_device >= 0 && current_device < config.ndmas)
|
struct dma_controller *dma = dat;
|
config.dmas[current_device].vapi_id = val.int_val;
|
dma->vapi_id = val.int_val;
|
else
|
}
|
CONFIG_ERROR("invalid device number.");
|
|
|
void *dma_sec_start(void)
|
|
{
|
|
struct dma_controller *new = malloc(sizeof(struct dma_controller));
|
|
|
|
if(!new) {
|
|
fprintf(stderr, "Peripheral DMA: Run out of memory\n");
|
|
exit(-1);
|
|
}
|
|
|
|
new->next = NULL;
|
|
|
|
return new;
|
|
}
|
|
|
|
void dma_sec_end(void *dat)
|
|
{
|
|
struct dma_controller *dma = dat;
|
|
struct dma_controller *cur;
|
|
|
|
register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, 0, dma_read32, dma_write32, dat );
|
|
reg_sim_reset( dma_reset, dat );
|
|
reg_sim_stat( dma_status, dat );
|
|
|
|
if(dmas) {
|
|
for(cur = dmas; cur->next; cur = cur->next);
|
|
cur->next = dma;
|
|
} else
|
|
dmas = dma;
|
}
|
}
|
|
|
void reg_dma_sec(void)
|
void reg_dma_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("dma", NULL, NULL);
|
struct config_section *sec = reg_config_sec("dma", dma_sec_start, dma_sec_end);
|
|
|
reg_config_param(sec, "ndmas", paramt_int, dma_ndmas);
|
|
reg_config_param(sec, "device", paramt_int, change_device);
|
|
reg_config_param(sec, "enddevice", paramt_none, end_device);
|
|
reg_config_param(sec, "irq", paramt_int, dma_irq);
|
reg_config_param(sec, "irq", paramt_int, dma_irq);
|
reg_config_param(sec, "baseaddr", paramt_addr, dma_baseaddr);
|
reg_config_param(sec, "baseaddr", paramt_addr, dma_baseaddr);
|
reg_config_param(sec, "vapi_id", paramt_addr, dma_vapi_id);
|
reg_config_param(sec, "vapi_id", paramt_addr, dma_vapi_id);
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
