| Line 26... |
Line 26... |
#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <errno.h>
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#include <errno.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#endif
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#include "port.h"
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#include "arch.h"
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "stats.h"
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#include "stats.h"
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| Line 39... |
Line 47... |
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/* Data cache */
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/* Data cache */
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struct dc_set {
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struct dc_set {
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struct {
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struct {
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unsigned long line[MAX_DC_BLOCK_SIZE];
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uint32_t line[MAX_DC_BLOCK_SIZE];
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unsigned long tagaddr; /* tag address */
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oraddr_t tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[MAX_DC_WAYS];
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} way[MAX_DC_WAYS];
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} dc[MAX_DC_SETS];
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} dc[MAX_DC_SETS];
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void dc_info()
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void dc_info()
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| Line 68... |
Line 76... |
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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- refill cache line
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- refill cache line
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*/
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*/
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unsigned long dc_simulate_read(unsigned long dataaddr, int width)
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uint32_t dc_simulate_read(oraddr_t dataaddr, int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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oraddr_t tagaddr;
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unsigned long tmp;
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uint32_t tmp;
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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data_ci) {
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data_ci) {
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if (width == 4)
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if (width == 4)
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tmp = evalsim_mem32(dataaddr);
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tmp = evalsim_mem32(dataaddr);
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else if (width == 2)
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else if (width == 2)
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tmp = (unsigned long)evalsim_mem16(dataaddr);
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tmp = evalsim_mem16(dataaddr);
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else if (width == 1)
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else if (width == 1)
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tmp = (unsigned long)evalsim_mem8(dataaddr);
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tmp = evalsim_mem8(dataaddr);
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if(!cur_area) {
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if(!cur_area) {
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if (width == 4)
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if (width == 4)
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printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", dataaddr);
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printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
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dataaddr);
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else if (width == 2)
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else if (width == 2)
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printf("EXCEPTION: read out of memory (16-bit access to %.8lx)\n", dataaddr);
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printf("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
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dataaddr);
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else if (width == 1)
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else if (width == 1)
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printf("EXCEPTION: read out of memory (8-bit access to %.8lx)\n", dataaddr);
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printf("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
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dataaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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return 0;
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return 0;
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}
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}
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if (!pending.valid && cur_area->log)
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if (!pending.valid && cur_area->log)
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fprintf (cur_area->log, "[%08lx] -> read %08lx\n", dataaddr, tmp);
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fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
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tmp);
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return tmp;
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return tmp;
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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| Line 125... |
Line 137... |
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2) {
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else if (width == 2) {
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tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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return tmp;
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return tmp;
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}
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}
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else if (width == 1) {
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else if (width == 1) {
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tmp = (unsigned long)((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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tmp = ((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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return tmp;
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return tmp;
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}
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}
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} else { /* No, we didn't. */
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} else { /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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| Line 151... |
Line 163... |
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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if(!cur_area) {
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if(!cur_area) {
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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dc[set].way[minway].lru = 0;
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printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", dataaddr);
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printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
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dataaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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return 0;
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return 0;
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}
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}
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if (!pending.valid && cur_area->log)
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if (!pending.valid && cur_area->log)
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fprintf (cur_area->log, "[%08lx] -> read %08lx\n", dataaddr, tmp);
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fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
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tmp);
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}
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}
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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| Line 170... |
Line 184... |
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tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2) {
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else if (width == 2) {
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tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff;
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return tmp;
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return tmp;
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}
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}
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else if (width == 1) {
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else if (width == 1) {
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tmp = (unsigned long)((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
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return tmp;
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return tmp;
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}
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}
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}
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}
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}
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}
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| Line 191... |
Line 205... |
- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void dc_simulate_write(unsigned long dataaddr, unsigned long data, int width)
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void dc_simulate_write(oraddr_t dataaddr, uint32_t data, int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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oraddr_t tagaddr;
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unsigned long tmp;
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uint32_t tmp;
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if (width == 4)
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if (width == 4)
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setsim_mem32(dataaddr, data);
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setsim_mem32(dataaddr, data);
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else if (width == 2)
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else if (width == 2)
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setsim_mem16(dataaddr, (unsigned short)data);
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setsim_mem16(dataaddr, data);
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else if (width == 1)
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else if (width == 1)
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setsim_mem8(dataaddr, (unsigned char)data);
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setsim_mem8(dataaddr, data);
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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data_ci ||
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data_ci ||
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(!cur_area))
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(!cur_area))
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| Line 235... |
Line 249... |
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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tmp = data;
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tmp = data;
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else if (width == 2) {
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else if (width == 2) {
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tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
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tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
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tmp |= (unsigned long)(data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
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tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
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}
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}
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else if (width == 1) {
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else if (width == 1) {
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tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
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tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
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tmp |= (unsigned long)(data & 0xff) << (8 * (3 - (dataaddr & 3)));
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tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3)));
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}
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}
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp;
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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| Line 277... |
Line 291... |
/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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otherwise don't do anything.
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otherwise don't do anything.
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*/
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*/
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void dc_inv(unsigned long dataaddr)
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void dc_inv(oraddr_t dataaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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oraddr_t tagaddr;
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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| Line 309... |
Line 323... |
dc[set].way[way].tagaddr = -1;
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dc[set].way[way].tagaddr = -1;
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dc[set].way[way].lru = 0;
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dc[set].way[way].lru = 0;
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}
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}
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}
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}
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inline void dc_clock()
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void dc_clock()
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{
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{
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unsigned long addr;
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oraddr_t addr;
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if ((addr = mfspr(SPR_DCBPR))) {
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if ((addr = mfspr(SPR_DCBPR))) {
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dc_simulate_read(addr, 4);
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dc_simulate_read(addr, 4);
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mtspr(SPR_DCBPR, 0);
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mtspr(SPR_DCBPR, 0);
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}
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}
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