| Line 347... |
Line 347... |
if ((addr = mfspr(SPR_DCBLR))) {
|
if ((addr = mfspr(SPR_DCBLR))) {
|
mtspr(SPR_DCBLR, 0);
|
mtspr(SPR_DCBLR, 0);
|
}
|
}
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
|
/*-----------------------------------------------------[ DC configuration ]---*/
|
|
void dc_enabled(union param_val val, void *dat)
|
|
{
|
|
config.dc.enabled = val.int_val;
|
|
setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0);
|
|
}
|
|
|
|
void dc_nsets(union param_val val, void *dat)
|
|
{
|
|
if (is_power2(val.int_val) && val.int_val <= MAX_DC_SETS)
|
|
config.dc.nsets = val.int_val;
|
|
else {
|
|
char tmp[200];
|
|
sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_DC_SETS);
|
|
CONFIG_ERROR(tmp);
|
|
}
|
|
}
|
|
|
|
void dc_nways(union param_val val, void *dat)
|
|
{
|
|
if (val.int_val >= 1 && val.int_val <= MAX_DC_WAYS)
|
|
config.dc.nways = val.int_val;
|
|
else
|
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
|
}
|
|
|
|
void dc_blocksize(union param_val val, void *dat)
|
|
{
|
|
if (is_power2(val.int_val))
|
|
config.dc.blocksize = val.int_val;
|
|
else
|
|
CONFIG_ERROR("value of power of two expected.");
|
|
}
|
|
|
|
void dc_ustates(union param_val val, void *dat)
|
|
{
|
|
if (val.int_val >= 2 && val.int_val <= 4)
|
|
config.dc.ustates = val.int_val;
|
|
else
|
|
CONFIG_ERROR("invalid USTATE.");
|
|
}
|
|
|
|
void dc_load_missdelay(union param_val val, void *dat)
|
|
{
|
|
config.dc.load_missdelay = val.int_val;
|
|
}
|
|
|
|
void dc_load_hitdelay(union param_val val, void *dat)
|
|
{
|
|
config.dc.load_hitdelay = val.int_val;
|
|
}
|
|
|
|
void dc_store_missdelay(union param_val val, void *dat)
|
|
{
|
|
config.dc.store_missdelay = val.int_val;
|
|
}
|
|
|
|
void dc_store_hitdelay(union param_val val, void *dat)
|
|
{
|
|
config.dc.store_hitdelay = val.int_val;
|
|
}
|
|
|
|
void reg_dc_sec(void)
|
|
{
|
|
struct config_section *sec = reg_config_sec("dc", NULL, NULL);
|
|
|
|
reg_config_param(sec, "enabled", paramt_int, dc_enabled);
|
|
reg_config_param(sec, "nsets", paramt_int, dc_nsets);
|
|
reg_config_param(sec, "nways", paramt_int, dc_nways);
|
|
reg_config_param(sec, "blocksize", paramt_int, dc_blocksize);
|
|
reg_config_param(sec, "ustates", paramt_int, dc_ustates);
|
|
reg_config_param(sec, "load_missdelay", paramt_int, dc_load_missdelay);
|
|
reg_config_param(sec, "load_hitdelay", paramt_int, dc_load_hitdelay);
|
|
reg_config_param(sec, "store_missdelay", paramt_int, dc_store_missdelay);
|
|
reg_config_param(sec, "store_hitdelay", paramt_int, dc_store_hitdelay);
|
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
