URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [cache/] [dcache_model.c] - Diff between revs 1382 and 1386

Rev 1382	Rev 1386
Line 105...	Line 105...
`else if (width == 1)`	`else if (width == 1)`
`printf("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",`	`printf("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",`
`dataaddr);`	`dataaddr);`
`except_handle(EXCEPT_BUSERR, cur_vadd);`	`except_handle(EXCEPT_BUSERR, cur_vadd);`
`return 0;`	`return 0;`
`}`	`} else if (cur_area->log)`

`if (!pending.valid && cur_area->log)`
`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,`	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,`
`tmp);`	`tmp);`

`return tmp;`	`return tmp;`
`}`	`}`
Line 167...	Line 165...
`dc[set].way[minway].lru = 0;`	`dc[set].way[minway].lru = 0;`
`printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`	`printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
`dataaddr);`	`dataaddr);`
`except_handle(EXCEPT_BUSERR, cur_vadd);`	`except_handle(EXCEPT_BUSERR, cur_vadd);`
`return 0;`	`return 0;`
`}`	`} else if (cur_area->log)`
`if (!pending.valid && cur_area->log)`
`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,`	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,`
`tmp);`	`tmp);`
`}`	`}`

`dc[set].way[minway].tagaddr = tagaddr;`	`dc[set].way[minway].tagaddr = tagaddr;`