| Line 31... |
Line 31... |
#include "dcache_model.h"
|
#include "dcache_model.h"
|
#include "abstract.h"
|
#include "abstract.h"
|
#include "stats.h"
|
#include "stats.h"
|
#include "spr_defs.h"
|
#include "spr_defs.h"
|
#include "sprs.h"
|
#include "sprs.h"
|
|
#include "sim-config.h"
|
|
|
/* Data cache */
|
/* Data cache */
|
|
|
/* Number of DC sets (power of 2) */
|
|
#define DC_SETS 512
|
|
|
|
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
|
|
#define DC_BLOCK_SIZE 16
|
|
|
|
/* Number of DC ways (1, 2, 3 etc.). */
|
|
#define DC_WAYS 1
|
|
|
|
/* Number of usage states (2, 3, 4 etc.). */
|
|
#define DC_USTATES 2
|
|
|
|
struct dc_set {
|
struct dc_set {
|
struct {
|
struct {
|
unsigned long tagaddr; /* tag address */
|
unsigned long tagaddr; /* tag address */
|
int lru; /* least recently used */
|
int lru; /* least recently used */
|
} way[DC_WAYS];
|
} way[MAX_DC_WAYS];
|
} dc[DC_SETS];
|
} dc[MAX_DC_SETS];
|
|
|
void dc_info()
|
void dc_info()
|
{
|
{
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
|
printf("DCache not implemented. Set UPR[DCP].\n");
|
printf("DCache not implemented. Set UPR[DCP].\n");
|
return;
|
return;
|
}
|
}
|
|
|
printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024);
|
printf("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
|
printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE);
|
printf("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- increment DC read hit stats,
|
- increment DC read hit stats,
|
- set 'lru' at this way to DC_USTATES - 1 and
|
- set 'lru' at this way to config.dc.ustates - 1 and
|
decrement 'lru' of other ways unless they have reached 0,
|
decrement 'lru' of other ways unless they have reached 0,
|
and if not:
|
and if not:
|
- increment DC read miss stats
|
- increment DC read miss stats
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
|
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dc_simulate_read(unsigned long dataaddr)
|
void dc_simulate_read(unsigned long dataaddr)
|
{
|
{
|
| Line 85... |
Line 74... |
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
|
return;
|
return;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dc_stats.readhit++;
|
dc_stats.readhit++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = DC_USTATES - 1;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
int minlru = DC_USTATES - 1;
|
int minlru = config.dc.ustates - 1;
|
int minway = 0;
|
int minway = 0;
|
|
|
dc_stats.readmiss++;
|
dc_stats.readmiss++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if ((dc[set].way[i].lru < minlru) &&
|
if ((dc[set].way[i].lru < minlru) &&
|
(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
|
(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
|
minway = i;
|
minway = i;
|
|
|
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = DC_USTATES - 1;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
}
|
}
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- increment DC write hit stats,
|
- increment DC write hit stats,
|
- set 'lru' at this way to DC_USTATES - 1 and
|
- set 'lru' at this way to config.dc.ustates - 1 and
|
decrement 'lru' of other ways unless they have reached 0,
|
decrement 'lru' of other ways unless they have reached 0,
|
and if not:
|
and if not:
|
- increment DC write miss stats
|
- increment DC write miss stats
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
|
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dc_simulate_write(unsigned long dataaddr)
|
void dc_simulate_write(unsigned long dataaddr)
|
{
|
{
|
| Line 142... |
Line 131... |
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
|
return;
|
return;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dc_stats.writehit++;
|
dc_stats.writehit++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = DC_USTATES - 1;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
int minlru = DC_USTATES - 1;
|
int minlru = config.dc.ustates - 1;
|
int minway = 0;
|
int minway = 0;
|
|
|
dc_stats.writemiss++;
|
dc_stats.writemiss++;
|
|
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if ((dc[set].way[i].lru < minlru) &&
|
if ((dc[set].way[i].lru < minlru) &&
|
(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
|
(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
|
minway = i;
|
minway = i;
|
|
|
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = DC_USTATES - 1;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
}
|
}
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- invalidate block if way isn't locked
|
- invalidate block if way isn't locked
|
| Line 193... |
Line 182... |
|
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
|
return;
|
return;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < DC_WAYS; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if ((way >= 0) && (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << way))) { /* Yes, we did. */
|
if ((way >= 0) && (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << way))) { /* Yes, we did. */
|
