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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [mmu/] [dmmu.c] - Diff between revs 430 and 438

Rev 430	Rev 438
Line 56...	Line 56...
`dmmu_stats.loads_tlbhit++;`	`dmmu_stats.loads_tlbhit++;`
`debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);`	`debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);`

`/* Test for page fault */`	`/* Test for page fault */`
`if (mfspr (SPR_SR) & SPR_SR_SUPV) {`	`if (mfspr (SPR_SR) & SPR_SR_SUPV) {`
`if ( write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SWE)`	`if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)`
`\|\| !write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SRE))`	`\|\| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))`
`except_handle(EXCEPT_DPF, virtaddr);`	`except_handle(EXCEPT_DPF, virtaddr);`
`} else {`	`} else {`
`if ( write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UWE)`	`if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)`
`\|\| !write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_URE))`	`\|\| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))`
`except_handle(EXCEPT_DPF, virtaddr);`	`except_handle(EXCEPT_DPF, virtaddr);`
`}`	`}`

`/* Set LRUs */`	`/* Set LRUs */`
`for (i = 0; i < config.dmmu.nways; i++)`	`for (i = 0; i < config.dmmu.nways; i++)`