| Line 46... |
Line 46... |
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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before a single character is transmitted or received. */
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before a single character is transmitted or received. */
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static unsigned long char_clks(int dll, int dlh, int lcr)
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static unsigned long char_clks(int dll, int dlh, int lcr)
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{
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{
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float bauds_per_char = 1.;
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float bauds_per_char = 1.;
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unsigned long char_clks = ((dlh << 8) + dll) * UART_CLOCK_DIVIDER;
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unsigned long char_clks = ((dlh << 8) + dll);
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if (lcr & UART_LCR_PARITY)
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if (lcr & UART_LCR_PARITY)
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bauds_per_char = bauds_per_char + 1.;
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bauds_per_char = bauds_per_char + 1.;
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/* stop bits 1 or two */
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/* stop bits 1 or two */
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| Line 330... |
Line 330... |
}
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}
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uarts[uart].regs.lsr |= UART_LSR_RDRDY;
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uarts[uart].regs.lsr |= UART_LSR_RDRDY;
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uarts[uart].istat.timeout_count = 0;
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uarts[uart].istat.timeout_count = 0;
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}
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}
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/* Reset. It initializes all registers of all UART devices to zero values,
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(re)opens all RX/TX file streams and places devices in memory address
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space. */
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void uart_reset()
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{
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int i;
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if (config.sim.verbose && config.nuarts)
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printf("Resetting %u UART(s).\n", config.nuarts);
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memset(uarts, 0, sizeof(uarts));
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for(i = 0; i < config.nuarts; i++) {
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if (config.uarts[i].vapi_id) {
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if ((config.uarts[i].vapi_id & VAPI_DEVICE_ID) != i) {
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fprintf (stderr, "ERROR: Wrong vapi_id (0x%x) for uart %i, last byte is required to be %02x; ignoring.\n", config.uarts[i].vapi_id, i, i);
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config.uarts[i].vapi_id = 0;
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uarts[i].txfs = 0;
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} else {
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vapi_install_handler (config.uarts[i].vapi_id, uart_vapi_read);
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register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte);
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}
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} else if (config.uarts[i].txfile) { /* MM: Try to create stream. */
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if (!(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r"))
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&& !(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r+"))) {
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debug (0, "WARNING: UART%d has problems with RX file stream.\n", i);
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continue;
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}
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uarts[i].txfs = fopen(config.uarts[i].txfile, "a");
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if (uarts[i].rxfs && uarts[i].txfs && config.sim.verbose) {
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printf("UART%d at 0x%.8x uses ", i, config.uarts[i].baseaddr);
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printf("%s for RX and %s for TX.\n", config.uarts[i].rxfile, config.uarts[i].txfile);
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} else
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debug (1, "WARNING: UART%d has problems with TX file stream.\n", i);
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register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte);
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}
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if (config.uarts[i].uart16550)
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uarts[i].fifo_len = 16;
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else
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uarts[i].fifo_len = 1;
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uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
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uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
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uarts[i].istat.break_set = 0;
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uarts[i].istat.timeout_count = 0;
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uarts[i].istat.thre_int = 1; /* FIFO is empty at start */
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uarts[i].slowdown = UART_FGETC_SLOWDOWN;
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uarts[i].regs.lcr = UART_LCR_RESET;
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uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
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uarts[i].vapi.next_break_cnt = -1;
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}
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}
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|
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/* Simulation hook. Must be called every clock cycle to simulate all UART
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
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devices. It does internal functional UART simulation. */
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devices. It does internal functional UART simulation. */
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void uart_clock()
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void uart_clock16(int i)
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{
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{
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int i, retval;
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int retval;
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|
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for(i = 0; i < config.nuarts; i++) {
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/* If VAPI is not selected, UART communicates with two file streams;
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/* If VAPI is not selected, UART communicates with two file streams;
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if VAPI is selected, we use VAPI streams. */
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if VAPI is selected, we use VAPI streams. */
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|
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/* if txfs is corrupted, skip this uart. */
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/* if txfs is corrupted, skip this uart. */
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if (!config.uarts[i].vapi_id && !uarts[i].txfs) continue;
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if (!config.uarts[i].vapi_id && !uarts[i].txfs) return;
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|
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if (uarts[i].vapi.next_break_cnt >= 0)
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if (uarts[i].vapi.next_break_cnt >= 0)
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if (--uarts[i].vapi.next_break_cnt < 0) {
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if (--uarts[i].vapi.next_break_cnt < 0) {
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if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
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if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
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uarts[i].istat.break_set = 0;
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uarts[i].istat.break_set = 0;
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| Line 494... |
Line 436... |
} else uarts[i].slowdown = UART_FGETC_SLOWDOWN;
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} else uarts[i].slowdown = UART_FGETC_SLOWDOWN;
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}
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}
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} else { /* VAPI */
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} else { /* VAPI */
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int received = 0;
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int received = 0;
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/* do not handle commands while receiving */
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/* do not handle commands while receiving */
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if (uarts[i].istat.rxser_full)
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if (uarts[i].istat.rxser_full) return;
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break;
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while (!received) {
|
while (!received) {
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if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
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if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
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unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
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unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
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debug(4, "Handling: %08x (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
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debug(4, "Handling: %08x (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
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uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
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uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
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| Line 601... |
Line 542... |
}
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}
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if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
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if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
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debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
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debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
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report_interrupt(config.uarts[i].irq);
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report_interrupt(config.uarts[i].irq);
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}
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}
|
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SCHED_ADD (uart_clock16, i, cycles + UART_CLOCK_DIVIDER);
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}
|
|
|
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
|
(re)opens all RX/TX file streams and places devices in memory address
|
|
space. */
|
|
void uart_reset()
|
|
{
|
|
int i;
|
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if (config.sim.verbose && config.nuarts) printf("Resetting %u UART(s).\n", config.nuarts);
|
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memset(uarts, 0, sizeof(uarts));
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|
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for(i = 0; i < config.nuarts; i++) {
|
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if (config.uarts[i].vapi_id) {
|
|
if ((config.uarts[i].vapi_id & VAPI_DEVICE_ID) != i) {
|
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fprintf (stderr, "ERROR: Wrong vapi_id (0x%x) for uart %i, last byte is required to be %02x; ignoring.\n", config.uarts[i].vapi_id, i, i);
|
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config.uarts[i].vapi_id = 0;
|
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uarts[i].txfs = 0;
|
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} else {
|
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vapi_install_handler (config.uarts[i].vapi_id, uart_vapi_read);
|
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register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte);
|
|
}
|
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} else if (config.uarts[i].txfile) { /* MM: Try to create stream. */
|
|
if (!(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r"))
|
|
&& !(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r+"))) {
|
|
debug (0, "WARNING: UART%d has problems with RX file stream.\n", i);
|
|
continue;
|
|
}
|
|
uarts[i].txfs = fopen(config.uarts[i].txfile, "a");
|
|
if (uarts[i].rxfs && uarts[i].txfs && config.sim.verbose) {
|
|
printf("UART%d at 0x%.8x uses ", i, config.uarts[i].baseaddr);
|
|
printf("%s for RX and %s for TX.\n", config.uarts[i].rxfile, config.uarts[i].txfile);
|
|
} else
|
|
debug (1, "WARNING: UART%d has problems with TX file stream.\n", i);
|
|
register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte);
|
|
}
|
|
|
|
if (config.uarts[i].uart16550)
|
|
uarts[i].fifo_len = 16;
|
|
else
|
|
uarts[i].fifo_len = 1;
|
|
|
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
|
|
|
uarts[i].istat.break_set = 0;
|
|
uarts[i].istat.timeout_count = 0;
|
|
uarts[i].istat.thre_int = 1; /* FIFO is empty at start */
|
|
uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
|
|
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
|
uarts[i].vapi.next_break_cnt = -1;
|
|
SCHED_ADD (uart_clock16, i, cycles + UART_CLOCK_DIVIDER);
|
}
|
}
|
}
|
}
|
|
|
/* Print register values on stdout. */
|
/* Print register values on stdout. */
|
void uart_status()
|
void uart_status()
|
