| Line 352... |
Line 352... |
eth->mac_address[1] != eth->rx_buff[4] ||
|
eth->mac_address[1] != eth->rx_buff[4] ||
|
eth->mac_address[0] != eth->rx_buff[5])
|
eth->mac_address[0] != eth->rx_buff[5])
|
break;
|
break;
|
}
|
}
|
|
|
break;
|
|
}
|
|
|
|
eth->rx.packet_length = nread;
|
eth->rx.packet_length = nread;
|
eth->rx.bytes_left = nread;
|
eth->rx.bytes_left = nread;
|
eth->rx.bytes_read = 0;
|
eth->rx.bytes_read = 0;
|
|
|
debug (3, "RX - entering state WRITEFIFO\n");
|
debug (3, "RX - entering state WRITEFIFO\n");
|
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
|
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
|
|
|
break;
|
break;
|
|
}
|
|
break;
|
|
|
case ETH_RXSTATE_WRITEFIFO:
|
case ETH_RXSTATE_WRITEFIFO:
|
#if 1
|
#if 1
|
send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read] << 24) |
|
send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read] << 24) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
|
| Line 473... |
Line 472... |
unsigned i;
|
unsigned i;
|
|
|
if (!config.nethernets)
|
if (!config.nethernets)
|
return;
|
return;
|
|
|
if ( first_time ) {
|
if ( first_time )
|
memset( eths, 0, sizeof(eths) );
|
memset( eths, 0, sizeof(eths) );
|
first_time = 0;
|
|
}
|
|
|
|
for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
|
for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
|
struct eth_device *eth = &(eths[i]);
|
struct eth_device *eth = &(eths[i]);
|
|
|
eth->eth_number = i;
|
eth->eth_number = i;
|
eth_reset_controller( eth );
|
eth_reset_controller( eth );
|
|
if ( eth->baseaddr && first_time )
|
|
register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
|
}
|
}
|
|
|
|
if ( first_time )
|
|
first_time = 0;
|
}
|
}
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
static void eth_reset_controller(struct eth_device *eth)
|
static void eth_reset_controller(struct eth_device *eth)
|
{
|
{
|
| Line 592... |
Line 595... |
|
|
/* Initialize TX/RX status */
|
/* Initialize TX/RX status */
|
memset( &(eth->tx), 0, sizeof(eth->tx) );
|
memset( &(eth->tx), 0, sizeof(eth->tx) );
|
memset( &(eth->rx), 0, sizeof(eth->rx) );
|
memset( &(eth->rx), 0, sizeof(eth->rx) );
|
eth->rx.bd_index = eth->regs.tx_bd_num;
|
eth->rx.bd_index = eth->regs.tx_bd_num;
|
|
|
/* Register memory range */
|
|
register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
|
|
}
|
}
|
}
|
}
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
| Line 716... |
Line 716... |
printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
|
printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
|
return;
|
return;
|
}
|
}
|
|
|
switch( addr ) {
|
switch( addr ) {
|
case ETH_MODER: eth->regs.moder = value; return;
|
case ETH_MODER: eth->regs.moder = value; if (TEST_FLAG(value, ETH_MODER, RST)) eth_reset(); return;
|
case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
|
case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
|
case ETH_INT_MASK: eth->regs.int_mask = value; return;
|
case ETH_INT_MASK: eth->regs.int_mask = value; return;
|
case ETH_IPGT: eth->regs.ipgt = value; return;
|
case ETH_IPGT: eth->regs.ipgt = value; return;
|
case ETH_IPGR1: eth->regs.ipgr1 = value; return;
|
case ETH_IPGR1: eth->regs.ipgr1 = value; return;
|
case ETH_IPGR2: eth->regs.ipgr2 = value; return;
|
case ETH_IPGR2: eth->regs.ipgr2 = value; return;
|
