URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 103 |
Rev 123 |
| Line 22... |
Line 22... |
#define NR_UARTS 4 /* Number of UARTs simulated */
|
#define NR_UARTS 4 /* Number of UARTs simulated */
|
#define NONE 0
|
#define NONE 0
|
#define VIRTUAL 1
|
#define VIRTUAL 1
|
#define PHYSICAL 2
|
#define PHYSICAL 2
|
|
|
|
typedef struct MemoryBlock {
|
|
int address;
|
|
char* file;
|
|
struct MemoryBlock* next;
|
|
} MemoryBlock;
|
|
|
struct config {
|
struct config {
|
struct {
|
struct {
|
int tagtype;
|
int tagtype;
|
} dc;
|
} dc;
|
struct {
|
struct {
|
| Line 50... |
Line 56... |
int dependstats;/* Calculation of dependency statistics */
|
int dependstats;/* Calculation of dependency statistics */
|
int dependency; /* Calculation of dependency (implied by dependstats) */
|
int dependency; /* Calculation of dependency (implied by dependstats) */
|
int history; /* Instruction stream history remembered by the simulator */
|
int history; /* Instruction stream history remembered by the simulator */
|
int superscalar;/* "Superscalar" simulation */
|
int superscalar;/* "Superscalar" simulation */
|
int slp;
|
int slp;
|
|
int inhibit_server; /* Don't start up the JTAG proxy server */
|
|
int server_port; /* A user specified port number for services */
|
|
int pattern_mem; /* A user specified memory initialization pattern */
|
|
int random_mem; /* Initialize the memory with random values */
|
|
MemoryBlock* memory; /* New style memory initializer file (CZ) */
|
|
char* filename; /* Original Command Simulator file (CZ) */
|
};
|
};
|
|
|
extern struct config config;
|
extern struct config config;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.