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https://opencores.org/ocsvn/or1k/or1k/trunk
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| Rev 294 |
Rev 304 |
| Line 55... |
Line 55... |
struct {
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struct {
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unsigned long baseaddr;
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unsigned long baseaddr;
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unsigned irq;
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unsigned irq;
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} dmas[NR_DMAS];
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} dmas[NR_DMAS];
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int nethernets;
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int ethernets_enabled;
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struct {
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struct {
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unsigned long baseaddr;
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unsigned long baseaddr;
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unsigned dma; /* Which controller is this ethernet "connected" to */
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unsigned dma; /* Which controller is this ethernet "connected" to */
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unsigned tx_channel; /* DMA channel used for TX */
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unsigned tx_channel; /* DMA channel used for TX */
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unsigned rx_channel; /* DMA channel used for RX */
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unsigned rx_channel; /* DMA channel used for RX */
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Line 92... |
int hazards; /* dependency hazards analysis */
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int hazards; /* dependency hazards analysis */
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int history; /* instruction stream history analysis */
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int history; /* instruction stream history analysis */
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int dependstats; /* dependency statistics */
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int dependstats; /* dependency statistics */
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int dependency; /* not sure: same as dependency statistics? */
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int dependency; /* not sure: same as dependency statistics? */
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int slp; /* not sure: stack analisys? */
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int slp; /* not sure: stack analisys? */
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int btic_sim; /* branch prediction target insn cache analysis */
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int btic; /* branch prediction target insn cache analysis */
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int bpb; /* branch prediction buffer analysis */
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int bpb; /* branch prediction buffer analysis */
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} cpu;
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} cpu;
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struct {
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struct {
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int debug; /* Simulator debugging */
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int debug; /* Simulator debugging */
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