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https://opencores.org/ocsvn/or1k/or1k/trunk
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| Rev 306 |
Rev 310 |
| Line 42... |
Line 42... |
int clkcycle_ns; /* Clock cycle in nanoseconds */
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int clkcycle_ns; /* Clock cycle in nanoseconds */
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int nuarts;
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int nuarts;
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int uarts_enabled;
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int uarts_enabled;
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struct {
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struct {
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char rxfile[STR_SIZE]; /* File for RX */
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char rxfile[STR_SIZE]; /* Filename for RX */
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char txfile[STR_SIZE]; /* File for TX (required) */
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char txfile[STR_SIZE]; /* Filename for TX (required) */
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int jitter; /* CZ 250801 - in msecs...time to block */
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int jitter; /* CZ 250801 - in msecs...time to block */
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unsigned long baseaddr; /* Naturally aligned base address */
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unsigned long baseaddr; /* Naturally aligned base address */
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} uarts[NR_UARTS];
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} uarts[NR_UARTS];
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int ndmas;
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int ndmas;
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| Line 62... |
Line 62... |
struct {
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struct {
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unsigned long baseaddr;
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unsigned long baseaddr;
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unsigned dma; /* Which controller is this ethernet "connected" to */
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unsigned dma; /* Which controller is this ethernet "connected" to */
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unsigned tx_channel; /* DMA channel used for TX */
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unsigned tx_channel; /* DMA channel used for TX */
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unsigned rx_channel; /* DMA channel used for RX */
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unsigned rx_channel; /* DMA channel used for RX */
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char *rxfile;
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char rxfile[STR_SIZE]; /* Filename for RX */
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char *txfile;
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char txfile[STR_SIZE]; /* File for TX */
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} ethernets[NR_ETHERNETS];
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} ethernets[NR_ETHERNETS];
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struct {
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struct {
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int enabled; /* is MC enabled? */
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int enabled; /* is MC enabled? */
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unsigned long baseaddr; /* Naturally aligned base address */
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unsigned long baseaddr; /* Naturally aligned base address */
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