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https://opencores.org/ocsvn/or1k/or1k/trunk
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| Rev 629 |
Rev 631 |
| Line 121... |
Line 121... |
int missdelay; /* How much cycles does the miss cost */
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int missdelay; /* How much cycles does the miss cost */
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int hitdelay; /* How much cycles does the hit cost */
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int hitdelay; /* How much cycles does the hit cost */
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} dmmu;
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} dmmu;
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struct {
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struct {
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int tagtype;
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int enabled; /* Whether instruction cache is enabled */
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int enabled; /* Whether instruction cache is enabled */
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int nways; /* Number of IC ways */
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int nways; /* Number of IC ways */
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int nsets; /* Number of IC sets */
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int nsets; /* Number of IC sets */
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int blocksize; /* IC entry size */
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int blocksize; /* IC entry size */
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int ustates; /* number of IC usage states */
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int ustates; /* number of IC usage states */
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| Line 133... |
Line 132... |
int hitdelay; /* How much cycles does the hit cost */
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int hitdelay; /* How much cycles does the hit cost */
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} ic;
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} ic;
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struct {
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struct {
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int enabled; /* Whether data cache is enabled */
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int enabled; /* Whether data cache is enabled */
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int tagtype;
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int nways; /* Number of DC ways */
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int nways; /* Number of DC ways */
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int nsets; /* Number of DC sets */
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int nsets; /* Number of DC sets */
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int blocksize; /* DC entry size */
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int blocksize; /* DC entry size */
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int ustates; /* number of DC usage states */
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int ustates; /* number of DC usage states */
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int store_missdelay; /* How much cycles does the store miss cost */
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int store_missdelay; /* How much cycles does the store miss cost */
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