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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [sim.cfg] - Diff between revs 535 and 541

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Rev 535	Rev 541
Line 143...	Line 143...
`entrysize =`	`entrysize =`
`instruction entry size in bytes`	`instruction entry size in bytes`

`ustates =`	`ustates =`
`number of ITLB usage states (2, 3, 4 etc., max is 4)`	`number of ITLB usage states (2, 3, 4 etc., max is 4)`

	`hitdelay =`
	`number of cycles immu hit costs`

	`missdelay =`
	`number of cycles immu miss costs`
`*/`	`*/`

`section immu`	`section immu`
`enabled = 0`	`enabled = 0`
`nsets = 32`	`nsets = 32`
`nways = 1`	`nways = 1`
`pagesize = 8192`	`pagesize = 8192`
	`hitdelay = 0`
	`missdelay = 0`
`end`	`end`


`/* DMMU SECTION`	`/* DMMU SECTION`

Line 175...	Line 183...
`entrysize =`	`entrysize =`
`data entry size in bytes`	`data entry size in bytes`

`ustates =`	`ustates =`
`number of DTLB usage states (2, 3, 4 etc., max is 4)`	`number of DTLB usage states (2, 3, 4 etc., max is 4)`

	`hitdelay =`
	`number of cycles immu hit costs`

	`missdelay =`
	`number of cycles immu miss costs`
`*/`	`*/`

`section dmmu`	`section dmmu`
`enabled = 0`	`enabled = 0`
`nsets = 32`	`nsets = 32`
`nways = 1`	`nways = 1`
`pagesize = 8192`	`pagesize = 8192`
	`hitdelay = 0`
	`missdelay = 0`
`end`	`end`


`/* IC SECTION`	`/* IC SECTION`

Line 204...	Line 220...
`blocksize =`	`blocksize =`
`IC block size in bytes; must be power of two`	`IC block size in bytes; must be power of two`

`ustates =`	`ustates =`
`number of IC usage states (2, 3, 4 etc., max is 4)`	`number of IC usage states (2, 3, 4 etc., max is 4)`

	`hitdelay =`
	`number of cycles ic hit costs`

	`missdelay =`
	`number of cycles ic miss costs`
`*/`	`*/`

`section ic`	`section ic`
`enabled = 0`	`enabled = 0`
`nsets = 512`	`nsets = 512`
`nways = 1`	`nways = 1`
`blocksize = 16`	`blocksize = 16`
	`hitdelay = 0`
	`missdelay = 0`
`end`	`end`


`/* DC SECTION`	`/* DC SECTION`

Line 233...	Line 257...
`blocksize =`	`blocksize =`
`DC block size in bytes; must be power of two`	`DC block size in bytes; must be power of two`

`ustates =`	`ustates =`
`number of DC usage states (2, 3, 4 etc., max is 4)`	`number of DC usage states (2, 3, 4 etc., max is 4)`

	`load_hitdelay =`
	`number of cycles dc load hit costs`

	`load_missdelay =`
	`number of cycles dc load miss costs`

	`store_hitdelay =`
	`number of cycles dc load hit costs`

	`store_missdelay =`
	`number of cycles dc load miss costs`
`*/`	`*/`

`section dc`	`section dc`
`enabled = 0`	`enabled = 0`
`nsets = 512`	`nsets = 512`
`nways = 1`	`nways = 1`
`blocksize = 16`	`blocksize = 16`
	`load_hitdelay = 0`
	`load_missdelay = 0`
	`store_hitdelay = 0`
	`store_missdelay = 0`
`end`	`end`

`/* SIM SECTION`	`/* SIM SECTION`

`This section specifies how should sim behave.`	`This section specifies how should sim behave.`
Line 346...	Line 386...

`dependstats = 0/1`	`dependstats = 0/1`
`whether inter-instruction dependencies are calculated`	`whether inter-instruction dependencies are calculated`
`and displayed by simulator stats command.`	`and displayed by simulator stats command.`

`btic = 0/1`
`enable branch target instruction cache model`

`bpb = 0/1`
`enable branch prediction buffer model`

`sbp_bf_fwd = 0/1`
`whether static branch prediction for l.bf uses forward prediction`

`sbp_bnf_fwd = 0/1`
`whether static branch prediction for l.bnf uses forward prediction`

`raw_range =`	`raw_range =`
`range in cycles for raw register over time analysis, 0 = disabled`	`range in cycles for raw register over time analysis, 0 = disabled`
`*/`	`*/`

`section cpu`	`section cpu`
Line 377...	Line 405...
`sbp_bnf_fwd = 1`	`sbp_bnf_fwd = 1`
`raw_range = 0`	`raw_range = 0`
`end`	`end`


	`/* BPB SECTION`

	`This section specifies how branch prediction should behave.`

	`enabled = 0/1`
	`whether bpb is enabled`

	`btic = 0/1`
	`enable branch target instruction cache model`

	`sbp_bf_fwd = 0/1`
	`whether static branch prediction for l.bf uses forward prediction`

	`sbp_bnf_fwd = 0/1`
	`whether static branch prediction for l.bnf uses forward prediction`

	`hitdelay =`
	`number of cycles bpb hit costs`

	`missdelay =`
	`number of cycles bpb miss costs`
	`*/`

	`section bpb`
	`enabled = 0`
	`btic = 0`
	`sbp_bf_fwd = 0`
	`sbp_bnf_fwd = 0`
	`hitdelay = 0`
	`missdelay = 0`
	`end`


`/* DEBUG SECTION`	`/* DEBUG SECTION`

`This sections specifies how debug unit should behave.`	`This sections specifies how debug unit should behave.`

`enabled = 0/1`	`enabled = 0/1`

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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [sim.cfg] - Diff between revs 535 and 541