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#define DW 32 /* Data width of memory model generated by dumpverilog in bits */
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#define DW 32 /* Data width of memory model generated by dumpverilog in bits */
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#define DWQ (DW/8) /* Same as DW but units are bytes */
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#define DWQ (DW/8) /* Same as DW but units are bytes */
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#define DISWIDTH 25 /* Width of disassembled message in bytes */
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#define DISWIDTH 25 /* Width of disassembled message in bytes */
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#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR, DISWIDTH) "\n\
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#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR, DISWIDTH) "\n"\
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`include \"general.h\"\n\n\
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"include \"general.h\"\n\n"\
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`timescale 1ns/100ps\n\n\
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"`timescale 1ns/100ps\n\n"\
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// Simple dw-wide Sync SRAM with initial content generated by or1ksim.\n\
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"// Simple dw-wide Sync SRAM with initial content generated by or1ksim.\n"\
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// All control, data in and addr signals are sampled at rising clock edge \n\
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"// All control, data in and addr signals are sampled at rising clock edge \n"\
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// Data out is not registered. Address bits specify dw-word (narrowest \n\
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"// Data out is not registered. Address bits specify dw-word (narrowest \n"\
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// addressed data is not byte but dw-word !). \n
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"// addressed data is not byte but dw-word !). \n"\
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// There are still some bugs in generated output (dump word aligned regions)\n\n\
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"// There are still some bugs in generated output (dump word aligned regions)\n\n"\
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module %s(clk, data, addr, ce, we, disout);\n\n\
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"module %s(clk, data, addr, ce, we, disout);\n\n"\
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parameter dw = 32;\n\
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"parameter dw = 32;\n"\
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parameter amin = %d;\n\n\
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"parameter amin = %d;\n\n"\
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parameter amax = %d;\n\n\
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"parameter amax = %d;\n\n"\
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input clk;\n\
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"input clk;\n"\
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inout [dw-1:0] data;\n\
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"inout [dw-1:0] data;\n"\
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input [31:0] addr;\n\
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"input [31:0] addr;\n"\
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input ce;\n\
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"input ce;\n"\
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input we;\n\
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"input we;\n"\
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output [%d:0] disout;\n\n\
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"output [%d:0] disout;\n\n"\
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reg [%d:0] disout;\n\
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"reg [%d:0] disout;\n"\
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reg [dw-1:0] mem [amax:amin];\n\
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"reg [dw-1:0] mem [amax:amin];\n"\
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reg [%d:0] dis [amax:amin];\n\
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"reg [%d:0] dis [amax:amin];\n"\
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reg [dw-1:0] dataout;\n\
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"reg [dw-1:0] dataout;\n"\
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tri [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n\
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"tri [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n"\
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initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH-1, DISWIDTH-1, DISWIDTH-1
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"initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH-1, DISWIDTH-1, DISWIDTH-1
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#define OR1K_MEM_VERILOG_FOOTER "\n\
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#define OR1K_MEM_VERILOG_FOOTER "\n\
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end\n\n\
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end\n\n\
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always @(posedge clk) begin\n\
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always @(posedge clk) begin\n\
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if (ce && ~we) begin\n\
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if (ce && ~we) begin\n\
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