URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [tick/] [tick.c] - Diff between revs 332 and 333

Rev 332	Rev 333
Line 27...	Line 27...

`#include "tick.h"`	`#include "tick.h"`
`#include "../cpu/or1k/spr_defs.h"`	`#include "../cpu/or1k/spr_defs.h"`
`#include "pic.h"`	`#include "pic.h"`
`#include "sprs.h"`	`#include "sprs.h"`
	`#include "sim-config.h"`

`/* For mode 10 only: timer stops until we write into TTCR. */`	`/* For mode 10 only: timer stops until we write into TTCR. */`
`int tt_stopped = 0;`	`int tt_stopped = 0;`

`/* Reset. It initializes TTCR register. */`	`/* Reset. It initializes TTCR register. */`
Line 65...	Line 66...
`if ((ttcr & SPR_TTCR_PERIOD) == (ttmr & SPR_TTMR_PERIOD)) {`	`if ((ttcr & SPR_TTCR_PERIOD) == (ttmr & SPR_TTMR_PERIOD)) {`
`int mode = (ttmr & SPR_TTMR_M) >> 30; /* CZ 04/09/01 */`	`int mode = (ttmr & SPR_TTMR_M) >> 30; /* CZ 04/09/01 */`

`if (ttmr & SPR_TTMR_IE) {`	`if (ttmr & SPR_TTMR_IE) {`
`setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);`	`setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);`
`report_interrupt(INT_TICK);`	`report_interrupt(config.tick.irq);`
`}`	`}`

`/* Handle the modes properly.. CZ 04/09/01 */`	`/* Handle the modes properly.. CZ 04/09/01 */`
`switch(mode)`	`switch(mode)`
`{`	`{`