OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [tick/] [tick.c] - Diff between revs 728 and 802

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 728 Rev 802
Line 58... Line 58...
{
{
  int mode = (ttmr & SPR_TTMR_M) >> 30;
  int mode = (ttmr & SPR_TTMR_M) >> 30;
  /*debug (7, "tick_job%i, param %i\n", param, mode);*/
  /*debug (7, "tick_job%i, param %i\n", param, mode);*/
  switch (mode) {
  switch (mode) {
  case 1:
  case 1:
 
    if (!param) {
    sprs[SPR_TTCR] = ttcr = 0;
    sprs[SPR_TTCR] = ttcr = 0;
 
      cycles_start = cycles - ttcr;
 
      SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
 
    }
  case 2:
  case 2:
    if (ttmr & SPR_TTMR_IE) {
    if (ttmr & SPR_TTMR_IE) {
      setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);
      setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);
      if ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE)
      if ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE)
        except_handle(EXCEPT_TICK, mfspr(SPR_EEAR_BASE));
        except_handle(EXCEPT_TICK, mfspr(SPR_EEAR_BASE));
 
      else
 
        /* If TEE is currently not set we have to pend tick exception
 
           by rescheduling. */
 
        SCHED_ADD(tick_job, 1, cycles + 1);
    }
    }
    break;
    break;
  }
  }
}
}
 
 
Line 77... Line 85...
  unsigned mode = (ttmr & SPR_TTMR_M) >> 30;
  unsigned mode = (ttmr & SPR_TTMR_M) >> 30;
  /*debug (7, "ttcr = %08x\n", value);*/
  /*debug (7, "ttcr = %08x\n", value);*/
  ttcr = value;
  ttcr = value;
  /* Remove previous if it exists */
  /* Remove previous if it exists */
  SCHED_FIND_REMOVE(tick_job, 0);
  SCHED_FIND_REMOVE(tick_job, 0);
 
  SCHED_FIND_REMOVE(tick_job, 1);
  if (mode == 1 || mode == 2) {
  if (mode == 1 || mode == 2) {
    SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
    SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
    cycles_start = cycles - ttcr;
    cycles_start = cycles - ttcr;
  }
  }
}
}
Line 90... Line 99...
  /*debug (7, "ttmr = %08x\n", value);*/
  /*debug (7, "ttmr = %08x\n", value);*/
  ttmr = value;
  ttmr = value;
  /* Handle the modes properly. */
  /* Handle the modes properly. */
  switch((ttmr & SPR_TTMR_M) >> 30) {
  switch((ttmr & SPR_TTMR_M) >> 30) {
    case 0:    /* Timer is disabled */
    case 0:    /* Timer is disabled */
 
      SCHED_FIND_REMOVE(tick_job, 0);
 
      SCHED_FIND_REMOVE(tick_job, 1);
      break;
      break;
    case 1:    /* Timer should auto restart */
    case 1:    /* Timer should auto restart */
      sprs[SPR_TTCR] = ttcr = 0;
      sprs[SPR_TTCR] = ttcr = 0;
      cycles_start = cycles;
      cycles_start = cycles;
      SCHED_FIND_REMOVE(tick_job, 0);
      SCHED_FIND_REMOVE(tick_job, 0);
 
      SCHED_FIND_REMOVE(tick_job, 1);
      SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
      SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
      break;
      break;
    case 2:    /* Stop the timer when match */
    case 2:    /* Stop the timer when match */
      SCHED_FIND_REMOVE(tick_job, 0);
      SCHED_FIND_REMOVE(tick_job, 0);
 
      SCHED_FIND_REMOVE(tick_job, 1);
      break;
      break;
    case 3:    /* Timer keeps running -- do nothing*/
    case 3:    /* Timer keeps running -- do nothing*/
      break;
      break;
  }
  }
}
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.