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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 992 |
Rev 997 |
Line 47... |
Line 47... |
} dc[MAX_DC_SETS];
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} dc[MAX_DC_SETS];
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void dc_info()
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void dc_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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printf("DCache not implemented. Set UPR[DCP].\n");
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PRINTF("DCache not implemented. Set UPR[DCP].\n");
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return;
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return;
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}
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}
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printf("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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PRINTF("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
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PRINTF("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC read hit stats,
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- increment DC read hit stats,
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- set 'lru' at this way to config.dc.ustates - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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