| Line 180... |
Line 180... |
temp3 = PARAM2;
|
temp3 = PARAM2;
|
temp2 = PARAM1;
|
temp2 = PARAM1;
|
if (temp3)
|
if (temp3)
|
temp1 = temp2 / temp3;
|
temp1 = temp2 / temp3;
|
else {
|
else {
|
except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
|
except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
|
return;
|
return;
|
}
|
}
|
set_ov_flag (temp1);
|
set_ov_flag (temp1);
|
SET_PARAM0(temp1);
|
SET_PARAM0(temp1);
|
}
|
}
|
| Line 194... |
Line 194... |
temp3 = PARAM2;
|
temp3 = PARAM2;
|
temp2 = PARAM1;
|
temp2 = PARAM1;
|
if (temp3)
|
if (temp3)
|
temp1 = temp2 / temp3;
|
temp1 = temp2 / temp3;
|
else {
|
else {
|
except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
|
except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
|
return;
|
return;
|
}
|
}
|
set_ov_flag (temp1);
|
set_ov_flag (temp1);
|
SET_PARAM0(temp1);
|
SET_PARAM0(temp1);
|
/* runtime.sim.cycles += 16; */
|
/* runtime.sim.cycles += 16; */
|
| Line 226... |
Line 226... |
SET_PARAM0(temp1);
|
SET_PARAM0(temp1);
|
/* runtime.sim.cycles += 2; */
|
/* runtime.sim.cycles += 2; */
|
}
|
}
|
INSTRUCTION (l_bf) {
|
INSTRUCTION (l_bf) {
|
if (config.bpb.enabled) {
|
if (config.bpb.enabled) {
|
int fwd = (PARAM0 >= pc) ? 1 : 0;
|
int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
|
or1k_mstats.bf[flag][fwd]++;
|
or1k_mstats.bf[flag][fwd]++;
|
bpb_update(current->insn_addr, flag);
|
bpb_update(current->insn_addr, flag);
|
}
|
}
|
if (flag) {
|
if (flag) {
|
pcdelay = pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
btic_update(pcnext);
|
btic_update(pcnext);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
} else {
|
} else {
|
btic_update(pc);
|
btic_update(cpu_state.pc);
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_bnf) {
|
INSTRUCTION (l_bnf) {
|
if (config.bpb.enabled) {
|
if (config.bpb.enabled) {
|
int fwd = (PARAM0 >= pc) ? 1 : 0;
|
int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
|
or1k_mstats.bnf[!flag][fwd]++;
|
or1k_mstats.bnf[!flag][fwd]++;
|
bpb_update(current->insn_addr, flag == 0);
|
bpb_update(current->insn_addr, flag == 0);
|
}
|
}
|
if (flag == 0) {
|
if (flag == 0) {
|
pcdelay = pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
btic_update(pcnext);
|
btic_update(pcnext);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
} else {
|
} else {
|
btic_update(pc);
|
btic_update(cpu_state.pc);
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_j) {
|
INSTRUCTION (l_j) {
|
pcdelay = pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
}
|
}
|
INSTRUCTION (l_jal) {
|
INSTRUCTION (l_jal) {
|
pcdelay = pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
|
|
set_reg(LINK_REGNO, pc + 8);
|
set_reg(LINK_REGNO, cpu_state.pc + 8);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
if (config.sim.profile) {
|
if (config.sim.profile) {
|
struct label_entry *tmp;
|
struct label_entry *tmp;
|
if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay)))
|
if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
|
runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
|
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
|
|
tmp->name);
|
else
|
else
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
|
runtime.sim.cycles, pc + 8, pcdelay, pcdelay);
|
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
|
|
cpu_state.pc_delay);
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_jalr) {
|
INSTRUCTION (l_jalr) {
|
pcdelay = PARAM0;
|
cpu_state.pc_delay = PARAM0;
|
set_reg(LINK_REGNO, pc + 8);
|
set_reg(LINK_REGNO, cpu_state.pc + 8);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
}
|
}
|
INSTRUCTION (l_jr) {
|
INSTRUCTION (l_jr) {
|
pcdelay = PARAM0;
|
cpu_state.pc_delay = PARAM0;
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
if (config.sim.profile)
|
if (config.sim.profile)
|
fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
|
fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
|
pcdelay);
|
cpu_state.pc_delay);
|
}
|
}
|
INSTRUCTION (l_rfe) {
|
INSTRUCTION (l_rfe) {
|
pcnext = mfspr(SPR_EPCR_BASE);
|
pcnext = mfspr(SPR_EPCR_BASE);
|
mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
|
mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
|
}
|
}
|
