Line 41... |
Line 41... |
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_PC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
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#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
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#define SPR_DCCFGR (SPRGROUP_SYS + 5)
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#define SPR_ICCFGR (SPRGROUP_SYS + 6)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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Line 95... |
Line 103... |
#define SPR_DMR2 (SPRGROUP_D + 17)
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#define SPR_DMR2 (SPRGROUP_D + 17)
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#define SPR_DWCR0 (SPRGROUP_D + 18)
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#define SPR_DWCR0 (SPRGROUP_D + 18)
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#define SPR_DWCR1 (SPRGROUP_D + 19)
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#define SPR_DWCR1 (SPRGROUP_D + 19)
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#define SPR_DSR (SPRGROUP_D + 20)
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#define SPR_DSR (SPRGROUP_D + 20)
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#define SPR_DRR (SPRGROUP_D + 21)
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#define SPR_DRR (SPRGROUP_D + 21)
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#define SPR_DIR (SPRGROUP_D + 22)
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/* Performance counters group */
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/* Performance counters group */
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#define SPR_PCCR(N) (SPRGROUP_PC + (N))
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#define SPR_PCCR(N) (SPRGROUP_PC + (N))
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#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
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#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
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Line 149... |
Line 156... |
/*
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/*
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* Bit definitions for the Supervision Register
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* Bit definitions for the Supervision Register
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*
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*
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*/
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_PXR 0x00008000 /* Partial exception recognition */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_EP 0x00004000 /* Exception Prefix */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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Line 162... |
Line 169... |
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
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/*
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/*
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* Bit definitions for the Data MMU Control Register
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* Bit definitions for the Data MMU Control Register
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*
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*
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*/
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*/
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Line 230... |
Line 237... |
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
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#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
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#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
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#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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/*
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/*
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* Bit definitions for Data Cache Control register
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* Bit definitions for Data Cache Control register
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*
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*
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Line 257... |
Line 262... |
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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/* Bit results with SPR_DCR_CC mask */
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_EQUAL 0x00000001
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#define SPR_DCR_CC_LESS 0x00000002
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#define SPR_DCR_CC_LESSE 0x00000003
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#define SPR_DCR_CC_GREAT 0x00000004
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#define SPR_DCR_CC_GREATE 0x00000005
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#define SPR_DCR_CC_NEQUAL 0x00000006
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/* Bit results with SPR_DCR_CT mask */
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_LSEA 0x000000c0
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/*
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/*
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* Bit definitions for Debug Mode 1 register
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* Bit definitions for Debug Mode 1 register
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*
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*
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*/
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*/
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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Line 300... |
Line 323... |
*/
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*/
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#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DSR_LPINTE 0x00000010 /* Low priority interrupt exception */
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#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */
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#define SPR_DSR_AE 0x00000020 /* Alignment exception */
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#define SPR_DSR_AE 0x00000020 /* Alignment exception */
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#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DSR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_BE 0x00001000 /* Breakpoint exception */
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#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
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#define SPR_DSR_TE 0x00002000 /* Trap exception */
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/*
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/*
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* Bit definitions for Debug reason register
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* Bit definitions for Debug reason register
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*
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*
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*/
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*/
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#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
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#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
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#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
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#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
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#define SPR_DRR_LPINTE 0x00000010 /* Low priority interrupt exception */
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#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
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#define SPR_DRR_AE 0x00000020 /* Alignment exception */
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#define SPR_DRR_AE 0x00000020 /* Alignment exception */
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#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
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#define SPR_DRR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_BE 0x00001000 /* Breakpoint exception */
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#define SPR_DRR_TE 0x00001000 /* Trap exception */
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/*
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/*
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* Bit definitions for Performance counters mode registers
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* Bit definitions for Performance counters mode registers
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*
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*
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*/
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*/
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Line 353... |
Line 377... |
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/*
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/*
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* Bit definitions for the Power management register
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* Bit definitions for the Power management register
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*
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*
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*/
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*/
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#define SPR_PMR_SDF 0x00000001 /* Slow down factor */
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#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
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#define SPR_PMR_DME 0x00000002 /* Doze mode enable */
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#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
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#define SPR_PMR_SME 0x00000004 /* Sleep mode enable */
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#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
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#define SPR_PMR_DCGE 0x00000008 /* Dynamic clock gating enable */
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#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
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#define SPR_PMR_SUME 0x00000010 /* Suspend mode enable */
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#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
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/*
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/*
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* Bit definitions for PICMR
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* Bit definitions for PICMR
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*
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*
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*/
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*/
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Line 385... |
Line 409... |
*/
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*/
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_CR 0x40000000 /* Continuous Run */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_TTE 0x80000000 /* Tick Timer Enable */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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/*
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|
* l.nop constants
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*
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*/
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_REPORT 0x0002 /* Simple report */
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#define NOP_PRINTF 0x0003 /* Simprintf instruction */
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#define NOP_REPORT_FIRST 0x0400 /* Report with number */
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#define NOP_REPORT_LAST 0x03ff /* Report with number */
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No newline at end of file
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No newline at end of file
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