| Line 69... |
Line 69... |
void dc_simulate_read(unsigned long dataaddr)
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void dc_simulate_read(unsigned long dataaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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|
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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return;
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return;
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|
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/* Which set to check out? */
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/* Which set to check out? */
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| Line 90... |
Line 91... |
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = config.dc.ustates - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
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}
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mem_cycles += config.dc.load_hitdelay;
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else { /* No, we didn't. */
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} else { /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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|
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dc_stats.readmiss++;
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dc_stats.readmiss++;
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| Line 107... |
Line 108... |
dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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mem_cycles += config.dc.load_missdelay;
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}
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}
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}
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}
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|
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC write hit stats,
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- increment DC write hit stats,
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| Line 126... |
Line 128... |
void dc_simulate_write(unsigned long dataaddr)
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void dc_simulate_write(unsigned long dataaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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|
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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return;
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return;
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|
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/* Which set to check out? */
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/* Which set to check out? */
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| Line 147... |
Line 150... |
|
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = config.dc.ustates - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
|
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mem_cycles += config.dc.store_hitdelay;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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|
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| Line 164... |
Line 168... |
dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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|
mem_cycles += config.dc.store_missdelay;
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}
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}
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}
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}
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|
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
|
