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Line 29... |
#include <stdarg.h>
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#include <stdarg.h>
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#include "icache_model.h"
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#include "icache_model.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "sim-config.h"
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#include "spr_defs.h"
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/* Instruction cache */
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/* Instruction cache */
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/* Number of IC sets (power of 2) */
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/* Number of IC sets (power of 2) */
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#define IC_SETS 512
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#define IC_SETS 512
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Line 55... |
} way[IC_WAYS];
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} way[IC_WAYS];
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} ic[IC_SETS];
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} ic[IC_SETS];
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void ic_info()
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void ic_info()
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{
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{
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if (!getsprbits(SPR_UPR, SPR_UPR_ICP)) {
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printf("ICache not implemented. Set UPR[ICP].\n");
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return;
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}
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printf("Instruction cache %dKB: ", IC_SETS * IC_BLOCK_SIZE * IC_WAYS / 1024);
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printf("Instruction cache %dKB: ", IC_SETS * IC_BLOCK_SIZE * IC_WAYS / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", IC_WAYS, IC_SETS, IC_BLOCK_SIZE);
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printf("%d ways, %d sets, block size %d bytes\n", IC_WAYS, IC_SETS, IC_BLOCK_SIZE);
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}
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}
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/* First check if instruction is already in the cache and if it is:
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/* First check if instruction is already in the cache and if it is:
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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/* ICache simulation enabled/disabled. */
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if ((!getsprbits(SPR_UPR, SPR_UPR_ICP)) || (!getsprbits(SPR_SR, SPR_SR_ICE)))
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (fetchaddr / IC_BLOCK_SIZE) % IC_SETS;
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set = (fetchaddr / IC_BLOCK_SIZE) % IC_SETS;
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tagaddr = (fetchaddr / IC_BLOCK_SIZE) / IC_SETS;
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tagaddr = (fetchaddr / IC_BLOCK_SIZE) / IC_SETS;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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if (ic[set].way[i].lru < minlru)
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if (ic[set].way[i].lru < minlru)
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minway = i;
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minway = i;
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ic[set].way[minway].tagaddr = tagaddr;
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ic[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < IC_WAYS; i++)
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if (ic[set].way[i].lru)
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if ((ic[set].way[i].lru) &&
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[minway].lru = IC_USTATES - 1;
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ic[set].way[minway].lru = IC_USTATES - 1;
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}
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}
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}
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}
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No newline at end of file
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No newline at end of file
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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otherwise don't do anything.
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*/
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void ic_inv(unsigned long dataaddr)
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{
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int set, way = -1;
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int i;
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unsigned long tagaddr;
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if (!getsprbits(SPR_UPR, SPR_UPR_ICP))
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return;
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/* Which set to check out? */
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set = (dataaddr / IC_BLOCK_SIZE) % IC_SETS;
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tagaddr = (dataaddr / IC_BLOCK_SIZE) / IC_SETS;
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < IC_WAYS; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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/* Did we find our cached data? */
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if ((way >= 0) && (getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << way))) { /* Yes, we did. */
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ic[set].way[way].tagaddr = -1;
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}
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}
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void ic_clock()
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{
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unsigned long addr;
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if (addr = mfspr(SPR_ICBPR)) {
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ic_simulate_read(addr);
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mtspr(SPR_ICBPR, 0);
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}
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if (addr = mfspr(SPR_ICBIR)) {
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ic_inv(addr);
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mtspr(SPR_ICBIR, 0);
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}
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if (addr = mfspr(SPR_ICBLR)) {
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mtspr(SPR_ICBLR, 0);
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}
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}
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No newline at end of file
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