| Line 68... |
Line 68... |
void ic_simulate_fetch(unsigned long fetchaddr)
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void ic_simulate_fetch(unsigned long fetchaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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/* ICache simulation enabled/disabled. */
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/* ICache simulation enabled/disabled. */
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)))
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return;
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return;
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| Line 90... |
Line 91... |
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for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].lru)
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if (ic[set].way[i].lru)
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[way].lru = config.ic.ustates - 1;
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ic[set].way[way].lru = config.ic.ustates - 1;
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mem_cycles += config.ic.hitdelay;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.ic.ustates - 1;
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int minlru = config.ic.ustates - 1;
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int minway = 0;
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int minway = 0;
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| Line 107... |
Line 109... |
for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if ((ic[set].way[i].lru) &&
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if ((ic[set].way[i].lru) &&
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[minway].lru = config.ic.ustates - 1;
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ic[set].way[minway].lru = config.ic.ustates - 1;
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mem_cycles += config.ic.missdelay;
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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