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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 550 |
Rev 554 |
Line 708... |
Line 708... |
cur_area->delayr = rd;
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cur_area->delayr = rd;
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if (config.memory.table[i].log[0] != '\0') {
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if (config.memory.table[i].log[0] != '\0') {
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if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
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if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
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fprintf (stderr, "WARNING: Cannot open '%s'.\n", config.memory.table[i].log);
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fprintf (stderr, "WARNING: Cannot open '%s'.\n", config.memory.table[i].log);
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} else
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} else
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cur_area->log = 0;
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cur_area->log = NULL;
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memory_needed += cur_area->size;
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memory_needed += cur_area->size;
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}
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}
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printf ("\n");
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printf ("\n");
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} else {
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} else {
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if (config.sim.verbose)
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if (config.sim.verbose)
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fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
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fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
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register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, &simmem_read_word, &simmem_write_word);
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register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, &simmem_read_word, &simmem_write_word);
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cur_area->misc = memory_needed;
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cur_area->chip_select = 0;
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cur_area->valid = 1;
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cur_area->delayw = 1;
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cur_area->delayr = 1;
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cur_area->log = NULL;
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memory_needed += cur_area->size;
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memory_needed += cur_area->size;
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}
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}
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simmem32 = (unsigned long *) malloc (sizeof (unsigned long) * ((memory_needed + 3) / 4));
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simmem32 = (unsigned long *) malloc (sizeof (unsigned long) * ((memory_needed + 3) / 4));
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if (!simmem32) {
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if (!simmem32) {
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