OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [cpu/] [common/] [stats.c] - Diff between revs 556 and 558

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 556 Rev 558
Line 196... Line 196...
    printf("DMMU read:  hit %d(%d%%), miss %d\n", dmmu_stats.loads_tlbhit, (dmmu_stats.loads_tlbhit * 100) / SD(dmmu_stats.loads_tlbhit + dmmu_stats.loads_tlbmiss), dmmu_stats.loads_tlbmiss);
    printf("DMMU read:  hit %d(%d%%), miss %d\n", dmmu_stats.loads_tlbhit, (dmmu_stats.loads_tlbhit * 100) / SD(dmmu_stats.loads_tlbhit + dmmu_stats.loads_tlbmiss), dmmu_stats.loads_tlbmiss);
  } else
  } else
    printf("No DMMU. Set UPR[DMP]\n");
    printf("No DMMU. Set UPR[DMP]\n");
 
 
  {
  {
    extern int loadcycles, storecycles, nops, nop_maxperiod;
    extern int loadcycles, storecycles;
    printf("Additional LOAD CYCLES: %u  STORE CYCLES: %u\n", loadcycles, storecycles);
    printf("Additional LOAD CYCLES: %u  STORE CYCLES: %u\n", loadcycles, storecycles);
    printf("l.nop  count: %u  maxgap: %u\n", nops, nop_maxperiod);
 
  }
  }
}
}
 
 
void printstats(int which)
void printstats(int which)
{
{

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.