| Line 529... |
Line 529... |
GEN ("\n/* Memory stores */\n");
|
GEN ("\n/* Memory stores */\n");
|
GEN ("always @(s_stb");
|
GEN ("always @(s_stb");
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if (f->mtype[i] & MT_STORE) {
|
if (f->mtype[i] & MT_STORE) {
|
char t[30];
|
char t[30];
|
unsigned long opt = f->INSN(f->msched[i]).opt[j];
|
unsigned long opt = f->INSN(f->msched[i]).opt[0];
|
if ((opt & ~OPT_DEST) != OPT_CONST) {
|
if ((opt & ~OPT_DEST) != OPT_CONST) {
|
GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
|
GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
|
}
|
}
|
}
|
}
|
|
|
| Line 549... |
Line 549... |
GEN (" else s_dat_o = 32'hx;\n");
|
GEN (" else s_dat_o = 32'hx;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
|
|
/* Generate load and store state machine */
|
/* Generate load and store state machine */
|
|
GEN ("\n/* Load&store state machine */\n");
|
|
GEN ("always @(posedge clk or posedge rst)\n");
|
|
GEN (" if (rst) begin\n");
|
|
if (nloads) GEN (" l_stb <= #Tp %i'h0;\n", nloads);
|
|
if (nstores) GEN (" s_stb <= #Tp %i'h0;\n", nstores);
|
|
GEN (" end else begin\n");
|
|
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
|
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
|
GEN (" if (");
|
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
|
GEN (") begin\n");
|
|
print_turn_off_dep (fo, f, dep);
|
|
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
|
|
GEN (" end\n");
|
|
}
|
|
GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
|
|
GEN (" end\n");
|
|
|
|
/* Generate state generator machine */
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++) {
|
char c;
|
char c;
|
char *s;
|
char *s;
|
|
|
switch (j) {
|
switch (j) {
|
| Line 563... |
Line 583... |
if (j == 0 && nloads
|
if (j == 0 && nloads
|
|| j == 1 && nstores
|
|| j == 1 && nstores
|
|| j == 2 && ncalls) {
|
|| j == 2 && ncalls) {
|
int cur = 0;
|
int cur = 0;
|
char t[30];
|
char t[30];
|
GEN ("\n/* %s state machine */\n", s);
|
|
GEN ("always @(posedge clk or posedge rst)\n");
|
|
GEN (" if (rst) %c_stb <= #Tp %i'h0;\n", c, j == 0 ? nloads : j == 1 ? nstores : ncalls);
|
|
GEN (" else begin\n");
|
|
for (i = 0; i < f->nmsched; i++)
|
|
if (j == 0 && f->mtype[i] & MT_LOAD
|
|
|| j == 1 && f->mtype[i] & MT_STORE
|
|
|| j == 2 && f->mtype[i] & MT_CALL) {
|
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
|
GEN (" if (");
|
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
|
GEN (") begin\n");
|
|
print_turn_off_dep (fo, f, dep);
|
|
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", c, cur++);
|
|
GEN (" end\n");
|
|
}
|
|
GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
|
|
GEN (" end\n");
|
|
|
|
GEN ("\n/* %s state generator machine */\n", s);
|
GEN ("\n/* %s state generator machine */\n", s);
|
GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < f->nmsched; i++) {
|
for (i = 0; i < f->nmsched; i++) {
|
print_op_v (f, t, f->msched[i], 1);
|
print_op_v (f, t, f->msched[i], 1);
|
| Line 732... |
Line 733... |
fprintf (stderr, "Cannot open '%s'\n", tmp);
|
fprintf (stderr, "Cannot open '%s'\n", tmp);
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
/* output header */
|
/* output header */
|
GEN ("/* %s -- generated by FLEXelerator\n", tmp);
|
GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
|
GEN (" (C) 2002 Flextronics http://www.flextronics.com/ */\n\n");
|
GEN (" (C) 2002 Marko Mlinar */\n\n");
|
GEN ("/* Includes %i functions:", nrf);
|
GEN ("/* Includes %i functions:", nrf);
|
for (i = 0; i < nfuncs; i++) if (f[i])
|
for (i = 0; i < nfuncs; i++) if (f[i])
|
GEN ("\n%s", prof_func[i].name);
|
GEN ("\n%s", prof_func[i].name);
|
GEN (" */\n\n");
|
GEN (" */\n\n");
|
|
|
