| Line 202... |
Line 202... |
assert (0);
|
assert (0);
|
return -1;
|
return -1;
|
}
|
}
|
|
|
/* Generates verilog file out of insn dataflow */
|
/* Generates verilog file out of insn dataflow */
|
void output_verilog (cuc_func *f, char *filename)
|
void output_verilog (cuc_func *f, char *filename, char *funcname)
|
{
|
{
|
FILE *fo;
|
FILE *fo;
|
int b, i, j;
|
int b, i, j;
|
int ci = 0, co = 0;
|
int ci = 0, co = 0;
|
int nloads = 0, nstores = 0, ncalls = 0;
|
int nloads = 0, nstores = 0, ncalls = 0;
|
| Line 227... |
Line 227... |
assert (end_bb && end_bb->type & BB_END);
|
assert (end_bb && end_bb->type & BB_END);
|
|
|
/* output header */
|
/* output header */
|
GEN ("/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
|
GEN ("/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
|
GEN (" (C) 2002 OpenCores http://www.opencores.org/\n");
|
GEN (" (C) 2002 OpenCores http://www.opencores.org/\n");
|
GEN (" function \"%s\"\n", filename);
|
GEN (" function \"%s\"\n", funcname);
|
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
|
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
|
GEN (" num BBs %i */\n\n", f->num_bb);
|
GEN (" num BBs %i */\n\n", f->num_bb);
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
|
