OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [mmu/] [dmmu.c] - Diff between revs 1344 and 1350

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1344 Rev 1350
Line 17... Line 17...
along with this program; if not, write to the Free Software
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* DMMU model (not functional yet, currently just copy of data cache). */
/* DMMU model (not functional yet, currently just copy of data cache). */
 
 
 
#include "config.h"
 
 
 
#ifdef HAVE_INTTYPES_H
 
#include <inttypes.h>
 
#endif
 
 
 
#include "port.h"
 
#include "arch.h"
#include "dmmu.h"
#include "dmmu.h"
#include "abstract.h"
#include "abstract.h"
#include "opcode/or32.h"
#include "opcode/or32.h"
#include "stats.h"
#include "stats.h"
#include "sprs.h"
#include "sprs.h"
Line 30... Line 38...
 
 
extern int cont_run;
extern int cont_run;
 
 
/* Data MMU */
/* Data MMU */
 
 
inline unsigned long dmmu_simulate_tlb(unsigned long virtaddr, int write_access)
inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)
{
{
  int set, way = -1;
  int set, way = -1;
  int i;
  int i;
  unsigned long tagaddr;
  oraddr_t tagaddr;
  unsigned long vpn, ppn;
  oraddr_t vpn, ppn;
 
 
  if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
  if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
    data_ci = (virtaddr >= 0x80000000);
    data_ci = (virtaddr >= 0x80000000);
    return virtaddr;
    return virtaddr;
  }
  }
Line 56... Line 64...
      way = i;
      way = i;
 
 
   /* Did we find our tlb entry? */
   /* Did we find our tlb entry? */
  if (way >= 0) { /* Yes, we did. */
  if (way >= 0) { /* Yes, we did. */
    dmmu_stats.loads_tlbhit++;
    dmmu_stats.loads_tlbhit++;
    debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);
    debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
 
 
    /* Test for page fault */
    /* Test for page fault */
    if (mfspr (SPR_SR) & SPR_SR_SM) {
    if (mfspr (SPR_SR) & SPR_SR_SM) {
      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
Line 122... Line 130...
 *
 *
 * RTRN: 0            - no DMMU, DMMU disabled or ITLB miss
 * RTRN: 0            - no DMMU, DMMU disabled or ITLB miss
 *       else         - appropriate PA (note it DMMU is not present
 *       else         - appropriate PA (note it DMMU is not present
 *                      PA === EA)
 *                      PA === EA)
 */
 */
unsigned long peek_into_dtlb(unsigned long virtaddr, int write_access,
oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
                            int through_dc)
 
{
{
  int set, way = -1;
  int set, way = -1;
  int i;
  int i;
  unsigned long tagaddr;
  oraddr_t tagaddr;
  unsigned long vpn, ppn;
  oraddr_t vpn, ppn;
 
 
  if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
  if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
    if (through_dc)
    if (through_dc)
      data_ci = (virtaddr >= 0x80000000);
      data_ci = (virtaddr >= 0x80000000);
    return virtaddr;
    return virtaddr;
Line 150... Line 157...
      way = i;
      way = i;
 
 
   /* Did we find our tlb entry? */
   /* Did we find our tlb entry? */
  if (way >= 0) { /* Yes, we did. */
  if (way >= 0) { /* Yes, we did. */
    dmmu_stats.loads_tlbhit++;
    dmmu_stats.loads_tlbhit++;
    debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);
    debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
 
 
    /* Test for page fault */
    /* Test for page fault */
    if (mfspr (SPR_SR) & SPR_SR_SM) {
    if (mfspr (SPR_SR) & SPR_SR_SM) {
      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
Line 184... Line 191...
  PRINTF("ERR, should never have happened\n");
  PRINTF("ERR, should never have happened\n");
  return(0);
  return(0);
}
}
 
 
 
 
unsigned long dmmu_translate(unsigned long virtaddr, int write_access)
oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
{
{
  unsigned long phyaddr = dmmu_simulate_tlb(virtaddr, write_access);
  oraddr_t phyaddr = dmmu_simulate_tlb(virtaddr, write_access);
 
 
/*  PRINTF("DMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
/*  PRINTF("DMMU translate(%"PRIxADDR") = %"PRIxADDR"\n", virtaddr, phyaddr);*/
  return phyaddr;
  return phyaddr;
}
}
 
 
 
 
void dtlb_info()
void dtlb_info()

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.