| Line 34... |
Line 34... |
#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(dmmu);
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extern int cont_run;
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extern int cont_run;
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/* Data MMU */
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/* Data MMU */
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inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)
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inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)
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| Line 64... |
Line 66... |
way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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| Line 106... |
Line 109... |
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
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#endif
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#endif
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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runtime.sim.mem_cycles += config.dmmu.missdelay;
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runtime.sim.mem_cycles += config.dmmu.missdelay;
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return 0;
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return 0;
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}
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}
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Line 162... |
way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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Line 192... |
}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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return(0);
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return(0);
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}
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}
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PRINTF("ERR, should never have happened\n");
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ERR("ERR, should never have happened\n");
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return(0);
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return(0);
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}
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}
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oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
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oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
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