| Line 69... |
Line 69... |
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dmmu_stats.loads_tlbhit++;
|
dmmu_stats.loads_tlbhit++;
|
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
runtime.sim.cycles);
|
runtime.sim.cycles);
|
|
|
/* Test for page fault */
|
|
if (mfspr (SPR_SR) & SPR_SR_SM) {
|
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
|
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
|
|
except_handle(EXCEPT_DPF, virtaddr);
|
|
} else {
|
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
|
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
|
|
except_handle(EXCEPT_DPF, virtaddr);
|
|
}
|
|
|
|
/* Set LRUs */
|
/* Set LRUs */
|
for (i = 0; i < config.dmmu.nways; i++)
|
for (i = 0; i < config.dmmu.nways; i++)
|
if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
|
if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
|
setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
|
setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
|
setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.nsets - 1);
|
setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.nsets - 1);
|
| Line 91... |
Line 80... |
/* Check if page is cache inhibited */
|
/* Check if page is cache inhibited */
|
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
|
|
runtime.sim.mem_cycles += config.dmmu.hitdelay;
|
runtime.sim.mem_cycles += config.dmmu.hitdelay;
|
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
|
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
|
|
|
|
/* Test for page fault */
|
|
if (mfspr (SPR_SR) & SPR_SR_SM) {
|
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
|
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
|
|
except_handle(EXCEPT_DPF, virtaddr);
|
|
} else {
|
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
|
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
|
|
except_handle(EXCEPT_DPF, virtaddr);
|
|
}
|
|
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
dmmu_stats.loads_tlbmiss++;
|
dmmu_stats.loads_tlbmiss++;
|
#if 0
|
#if 0
|
| Line 108... |
Line 109... |
setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
|
setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
|
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
|
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
|
setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
|
setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
|
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
|
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
|
#endif
|
#endif
|
except_handle(EXCEPT_DTLBMISS, virtaddr);
|
|
TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
runtime.sim.cycles);
|
runtime.sim.cycles);
|
|
runtime.sim.mem_cycles += config.dmmu.missdelay;
|
/* if tlb refill implemented in HW */
|
/* if tlb refill implemented in HW */
|
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
|
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
|
runtime.sim.mem_cycles += config.dmmu.missdelay;
|
except_handle(EXCEPT_DTLBMISS, virtaddr);
|
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
|
|
/* DESC: try to find EA -> PA transaltion without changing
|
/* DESC: try to find EA -> PA transaltion without changing
|
