| Line 34... |
Line 34... |
{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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unsigned long vpn, ppn;
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unsigned long vpn, ppn;
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extern int mem_cycles;
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|
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || (!testsprbits(SPR_SR, SPR_SR_DME)))
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || (!testsprbits(SPR_SR, SPR_SR_DME)))
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return virtaddr;
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return virtaddr;
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|
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/* Which set to check out? */
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/* Which set to check out? */
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| Line 71... |
Line 72... |
for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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|
|
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mem_cycles += config.dmmu.hitdelay;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.dmmu.ustates - 1;
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int minlru = config.dmmu.ustates - 1;
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| Line 95... |
Line 97... |
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
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setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
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#endif
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#endif
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
|
|
mem_cycles += config.dmmu.missdelay;
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return 0;
|
return 0;
|
}
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}
|
}
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}
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|
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unsigned long dmmu_translate(unsigned long virtaddr, int write_access)
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unsigned long dmmu_translate(unsigned long virtaddr, int write_access)
|
